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參數(shù)資料
| 型號： | K4H560838M-TLA2 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 元件分類： | 串行ADC |
| 英文描述： | 10-Bit, 38 kSPS ADC Serial Out, On-Chip System Clock, 11 Ch. 20-SOIC |
| 中文描述： | 128MB DDR SDRAM的 |
| 文件頁數(shù)： | 19/19頁 |
| 文件大?。?/td> | 171K |
| 代理商： | K4H560838M-TLA2 |
DDR SDRAM
DDR SDRAM 256Mb F-die (x8, x16)
Rev. 1.1 August. 2003
j. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser
on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter
mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions.
k. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi
tions through the DC region must be monotony.
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| K4H560838M-TLB0 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mb DDR SDRAM |
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