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參數(shù)資料
| 型號： | K4N56163QF-GC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mbit gDDR2 SDRAM |
| 中文描述： | 片256Mbit GDDR2 SDRAM的 |
| 文件頁數(shù)： | 15/73頁 |
| 文件大?。?/td> | 1262K |
| 代理商： | K4N56163QF-GC |
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- 15 -
Rev 1.6 (Apr. 2005)
256M gDDR2 SDRAM
K4N56163QF-GC
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between DQS - DQS = -500 mV
and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to VREF + 250 mV for rising
edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to CK - CK = +500 mV
(250mV to -500 mV for falling egdes).
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or between DQS and DQS
for differential strobe.
2. gDDR2 SDRAM AC timing reference load
Following figure represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to
be either a precise representation of the typical system environment or a depiction of the actual load presented by a production tester.
System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers
will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level
for differential signals is the crosspoint of the true (e.g. DQS) and the complement (e.g. DQS) signal.
Parameter
Symbol
- 25
- 30
- 37
Units
Notes
min
max
min
max
min
max
ODT turn-off
t
AOF
tAC
(min)
tAC
(max)+ 0.6
tAC
(min)
tAC
(max)+ 0.6
tAC
(min)
tAC
(max)+ 0.6
ns
26
ODT turn-off (Power-Down
mode)
t
AOFPD
tAC(min)+2
3.5tCK+tA
C(max)+1
tAC(min)+2
2.5tCK+tA
C(max)+1
tAC(min)+
2
2.5tCK+
tAC(max)+
1
ns
ODT to power down entry
latency
tANPD
3
3
3
tCK
ODT power down exit latency
tAXPD
8
8
8
tCK
OCD drive mode output delay
tOIT
0
12
0
12
0
12
ns
Minimum time clocks remains
ON after CKE
asynchronously drops LOW
tDelay
tIS+tCK
+tIH
tIS+tCK
+tIH
tIS+tCK
+tIH
ns
24
VDDQ
DUT
DQ
DQS
DQS
Output
V
TT
= V
DDQ
/2
25
Timing
reference
point
<AC Timing Reference Load>
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