參數(shù)資料
型號: K4S161622D
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 512K x 16Bit x 2 Banks Synchronous DRAM
中文描述: 為512k × 16 × 2銀行同步DRAM
文件頁數(shù): 4/41頁
文件大小: 1127K
代理商: K4S161622D
K4S161622D
CMOS SDRAM
1. Unless otherwise notes, Input level is CMOS(V
IH
/V
IL
=V
DDQ
/V
SSQ
) in LVTTL.
2. Measured with outputs open. Addresses are changed only one time during tcc(min).
3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).
4. K4S161622D-TC**
5. K4S161622D-TL**
Note :
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T
A
= 0 to 70
°
C)
Parameter
Symbol
Test Condition
CAS
Latency
Version
Unit
Note
-55
-60
-70
-80
-10
Operating Current
(One Bank Active)
I
CC1
Burst Length =1
t
RC
t
RC
(min)
I
o
= 0 mA
3
120
115
105
95
85
mA
2
2
-
-
110
95
80
Precharge Standby Cur-
rent in power-down mode
I
CC2
P
CKE
V
IL
(max), t
CC
= 15ns
2
mA
I
CC2
PS
CKE & CLK
V
IL
(max), t
CC
=
2
Precharge Standby Current
in non power-down mode
I
CC2
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
15
mA
I
CC2
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
5
Active Standby Current
in power-down mode
I
CC3
P
CKE
V
IL
(max), t
CC
= 15ns
3
mA
I
CC3
PS
CKE & CLK
V
IL
(max), t
CC
=
3
Active Standby Current
in non power-down mode
(One Bank Active)
I
CC3
N
CKE
V
IH
(min), CS
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
25
mA
I
CC3
NS
CKE
V
IH
(min), CLK
V
IL
(max), t
CC
=
Input signals are stable
15
mA
Operating Current
(Burst Mode)
I
CC4
I
o
= 0 mA
Page Burst 2Banks Activated
t
CCD
= 2CLKs
3
155
150
140
130
115
mA
2
2
-
-
125
115
100
Refresh Current
I
CC5
t
RC
t
RC
(min)
3
105
100
90
90
80
mA
3
2
-
-
100
90
80
Self Refresh Current
I
CC6
CKE
0.2V
1
mA
4
250
uA
5
相關PDF資料
PDF描述
K4S161622E 1M x 16 SDRAM
K4S161622E-TC10 1M x 16 SDRAM
K4S161622E-TC55 1M x 16 SDRAM
K4S161622E-TC60 1M x 16 SDRAM
K4S161622E-TC70 1M x 16 SDRAM
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