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| 型號(hào)： | K4S561632E-UL60 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Mb E-die SDRAM Specification 54 TSOP-II with Pb-Free (RoHS compliant) |
| 中文描述： | 256Mb的電子芯片與內(nèi)存規(guī)格鉛54 TSOP-II免費(fèi)（符合RoHS） |
| 文件頁(yè)數(shù)： | 14/14頁(yè) |
| 文件大?。?/td> | 198K |
| 代理商： | K4S561632E-UL60 |
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SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 August 2004
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA
0,1
A
10
/AP
A
0
~ A
9
A
11,
A
12
Note
Register
Mode register set
Auto refresh
H
X
H
L
L
L
L
L
X
OP code
1,2
3
3
3
3
Refresh
H
L
L
L
H
X
X
Self
refresh
Entry
Exit
L
H
L
H
L
H
X
L
H
X
H
H
X
H
X
X
Bank active & row addr.
Read &
column address
H
X
X
V
Row address
L
H
L
H
X
L
H
Auto precharge disable
Auto precharge enable
Auto precharge disable
Auto precharge enable
H
X
L
H
L
H
X
V
Column
address
4
4,5
4
4,5
6
Write &
column address
H
X
L
H
L
L
X
V
Column
address
Burst stop
H
X
L
H
H
L
X
Precharge
Bank selection
All banks
H
X
L
L
H
L
X
V
X
X
Clock suspend or
active power down
Entry
H
L
H
L
X
H
L
H
L
X
V
X
X
H
X
V
X
X
H
X
V
X
X
H
X
V
X
V
X
X
H
X
V
X
X
Exit
L
H
X
Precharge power down mode
Entry
H
L
X
X
Exit
L
H
X
DQM
H
V
X
7
No operation command
H
X
H
L
X
H
X
H
X
X
Notes :
1. OP Code : Operand code
A
0
~ A
12
& BA
0
~ BA
1
: Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA
0
~ BA
1
: Bank select addresses.
If both BA
0
and BA
1
are "Low" at read, write, row active and precharge, bank A is selected.
If BA
0
is "High" and BA
1
is "Low" at read, write, row active and precharge, bank B is selected.
If BA
0
is "Low" and BA
1
is "High" at read, write, row active and precharge, bank C is selected.
If both BA
0
and BA
1
are "High" at read, write, row active and precharge, bank D is selected.
If A
10
/AP is "High" at row precharge, BA
0
and BA
1
is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t
RP
after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
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