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參數(shù)資料
| 型號(hào)： | K4S643232H-TL55 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Mb H-die (x32) SDRAM Specification |
| 中文描述： | 64兆?芯片（X32號(hào)）內(nèi)存規(guī)格 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 118K |
| 代理商： | K4S643232H-TL55 |
CMOS SDRAM
- 11
SDRAM 64Mb H-die (x32)
Rev. 1.4 August 2004
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Note :
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
50
55
60
70
Unit
Note
Min
Max
Min
Max
Min
Max
Min
Max
CLK cycle time
CAS Latency=3
t
CC
5
1000
5.5
1000
6
1000
7
1000
ns
1
CAS Latency=2
10
10
10
10
CLK to valid
output delay
CAS Latency=3
t
SAC
-
4.5
-
5.0
-
5.5
-
5.5
ns
1, 2
CAS Latency=2
-
6
-
6
-
6
-
6
Output data hold time
t
OH
2
-
2
-
2
-
2
-
ns
2
CLK high pulse
width
CAS Latency=3
t
CH
2
-
2
-
2.5
-
3
-
ns
3
CAS Latency=2
3
-
3
-
3
-
3
-
CLK low
pulse width
CAS Latency=3
t
CL
2
-
2
-
2.5
-
3
-
ns
3
CAS Latency=2
3
-
3
-
3
-
3
-
Input setup time
CAS Latency=3
t
SS
1.5
-
1.5
-
1.5
-
1.75
-
ns
3
CAS Latency=2
2.5
-
2.5
-
2.5
-
2.5
-
Input hold time
t
SH
1
-
1
-
1
-
1
-
ns
3
CLK to output in Low-Z
t
SLZ
1
-
1
-
1
-
1
-
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
-
4.5
-
5.0
-
5.5
-
5.5
ns
-
CAS latency=2
-
6
-
6
-
6
-
6
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| K4S643232H-TL60 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die (x32) SDRAM Specification |
| K4S643232H-TL70 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mb H-die (x32) SDRAM Specification |
| K4S643232H-UC50 | 制造商:Samsung Semiconductor 功能描述: 制造商:Samsung Electro-Mechanics 功能描述:SDRAM, 2M x 32, 86 Pin, Plastic, TSSOP 制造商:Samsung Semiconductor 功能描述:SDRAM, 2M x 32, 86 Pin, Plastic, TSSOP |
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