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參數資料
| 型號： | K6R4004C1C-E10 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx4 Bit High Speed Static RAM(5V Operating). |
| 中文描述： | 1Mx4位高速靜態(tài)RAM（5V的工作）。 |
| 文件頁數： | 5/8頁 |
| 文件大小： | 155K |
| 代理商： | K6R4004C1C-E10 |
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
CMOS SRAM
PRELIMINARY
Rev 3.0
- 5 -
March 2000
WRITE CYCLE*
* The above parameters are also guaranteed at extended and industrial temperature range.
Parameter
Symbol
K6R4004C1C-10
K6R4004C1C-12
K6R4004C1C-15
K6R4004C1C-20
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Write Cycle Time
t
WC
10
-
12
-
15
-
20
-
ns
Chip Select to End of Write
t
CW
7
-
8
-
10
-
12
-
ns
Address Set-up Time
t
AS
0
-
0
-
0
-
0
-
ns
Address Valid to End of Write
t
AW
7
-
8
-
10
-
12
-
ns
Write Pulse Width(OE High)
t
WP
7
-
8
-
10
-
12
-
ns
Write Pulse Width(OE Low)
t
WP1
10
-
12
-
15
-
20
-
ns
Write Recovery Time
t
WR
0
-
0
-
0
-
0
-
ns
Write to Output High-Z
t
WHZ
0
5
0
6
0
7
0
9
ns
Data to Write Time Overlap
t
DW
5
-
6
-
7
-
9
-
ns
Data Hold from Write Time
t
DH
0
-
0
-
0
-
0
-
ns
End Write to Output Low-Z
t
OW
3
-
3
-
3
-
3
-
ns
Address
Data Out
Previous Valid Data
Valid Data
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1)
(Address Controlled
,
CS=OE=V
IL
, WE=V
IH
)
t
AA
t
RC
t
OH
TIMING WAVEFORM OF READ CYCLE(2)
(WE=V
IH
)
CS
Address
OE
Data ou
t
t
AA
t
OLZ
t
LZ(4,5)
t
OH
t
OHZ
t
RC
t
OE
t
CO
t
PU
t
PD
t
HZ(3,4,5)
50%
50%
V
CC
Current
I
CC
I
SB
Valid Data
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
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| K6R4004C1C-E12 | 1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-E15 | 1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-E20 | 1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-I | 1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-I10 | 1Mx4 Bit High Speed Static RAM(5V Operating). |
相關代理商/技術參數 |
參數描述 |
|---|---|
| K6R4004C1C-E12 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-E15 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-E20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-I | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx4 Bit High Speed Static RAM(5V Operating). |
| K6R4004C1C-I10 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1Mx4 Bit High Speed Static RAM(5V Operating). |
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