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參數(shù)資料
| 型號： | K6R4004C1D-JC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1Mx4 Bit High Speed Static RAM(3.3V Operating). Operated at Commercial and Industrial Temperature Ranges |
| 中文描述： | 1Mx4位高速靜態(tài)RAM（3.3V的）。在商用和工業(yè)溫度范圍運營 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大小： | 218K |
| 代理商： | K6R4004C1D-JC |
K6R4004V1D
CMOS SRAM
PRELIMINARY
Rev 2.0
July 2004
- 5 -
TEST CONDITIONS*
* The above test conditions are also applied at industrial temperature range.
Parameter
Value
Input Pulse Levels
0V to 3V
Input Rise and Fall Times
3ns
Input and Output timing Reference Levels
1.5V
Output Loads
See below
AC CHARACTERISTICS
(T
A
=0 to 70
°
C, V
CC
=3.3
±
0.3V, unless otherwise noted.)
Output Loads(B)
for t
HZ
, t
LZ
, t
WHZ
, t
OW
, t
OLZ
& t
OHZ
D
OUT
5pF*
319
353
+3.3V
* Including Scope and Jig Capacitance
Output Loads(A)
D
OUT
R
L
= 50
Z
O
= 50
V
L
= 1.5V
30pF*
* Capacitive Load consists of all components of the
test environment.
READ CYCLE*
* The above parameters are also guaranteed at industrial temperature range.
Parameter
Symbol
K6R4004V1D-08
K6R4004V1D-10
Unit
Min
Max
Min
Max
Read Cycle Time
t
RC
8
-
10
-
ns
Address Access Time
t
AA
-
8
-
10
ns
Chip Select to Output
t
CO
-
8
-
10
ns
Output Enable to Valid Output
t
OE
-
4
-
5
ns
Chip Enable to Low-Z Output
t
LZ
3
-
3
-
ns
Output Enable to Low-Z Output
t
OLZ
0
-
0
-
ns
Chip Disable to High-Z Output
t
HZ
0
4
0
5
ns
Output Disable to High-Z Output
t
OHZ
0
4
0
5
ns
Output Hold from Address Change
t
OH
3
-
3
-
ns
Chip Selection to Power Up Time
t
PU
0
-
0
-
ns
Chip Selection to Power DownTime
t
PD
-
8
-
10
ns
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