參數(shù)資料
型號: K6R4004C1D-KI10
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256Kx16 Bit High Speed Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges.
中文描述: 256Kx16位高速靜態(tài)RAM(5.0V操作)。在經(jīng)營商業(yè)和工業(yè)溫度范圍。
文件頁數(shù): 7/8頁
文件大小: 155K
代理商: K6R4004C1D-KI10
K6R4004C1C-C, K6R4004C1C-I, K6R4004C1C-E
CMOS SRAM
PRELIMINARY
Rev 3.0
- 7 -
March 2000
NOTES
(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS and WE. A write begins at the latest transition CS going low and WE going low ; A write
ends at the earliest transition CS going high or WE going high. t
WP
is measured from the beginning of write to the end of write.
3. t
CW i
s measured from the later of CS going low to end of write.
4. t
AS
is measured from the address valid to the beginning of write.
5. t
WR
is measured from the end of write to the address change. t
WR
applied in case a write ends as CS or WE going high.
6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the
output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
9. Dout is the read data of the new address.
10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
FUNCTIONAL DESCRIPTION
* X means Don
t Care.
CS
WE
OE
Mode
I/O Pin
Supply Current
H
X
X*
Not Select
High-Z
I
SB
, I
SB1
L
H
H
Output Disable
High-Z
I
CC
L
H
L
Read
D
OUT
I
CC
L
L
X
Write
D
IN
I
CC
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