參數(shù)資料
型號: K6R4016C1D-JL10
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256Kx16 Bit High Speed Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges.
中文描述: 256Kx16位高速靜態(tài)RAM(5.0V操作)。在經(jīng)營商業(yè)和工業(yè)溫度范圍。
文件頁數(shù): 8/12頁
文件大小: 139K
代理商: K6R4016C1D-JL10
K6R4016C1D
CMOS SRAM
PRELIMPreliminaryPPPPPPPPPINARY
Rev 2.0
June 2003
- 8 -
NOTES
(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ
and t
OHZ
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
OH
or V
OL
levels.
4. At any given temperature and voltage condition, t
HZ
(Max.) is less than t
LZ
(Min.) both for a given device and from device to
device.
5. Transition is measured
±
200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
IL.
7. Address valid prior to coincident with CS transition low.
8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1)
(OE Clock)
Address
CS
UB, LB
WE
Data in
Data out
t
WC
t
CW(3)
t
BW
t
WP(2)
t
AS(4)
t
DH
t
DW
t
OHZ(6)
High-Z
High-Z
Valid Data
OE
t
AW
t
WR(5)
TIMING WAVEFORM OF WRITE CYCLE(2)
(OE=Low fixed)
Address
CS
UB, LB
WE
Data in
Data out
t
WC
t
CW(3)
t
BW
t
WP1(2)
t
DH
t
DW
t
WR(5)
t
AS(4)
t
OW
t
WHZ(6)
(10)
(9)
High-Z
Valid Data
t
AW
High-Z
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