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參數(shù)資料
| 型號： | K7A803609A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 256Kx36 & 512Kx18 Synchronous SRAM |
| 中文描述： | 256Kx36 |
| 文件頁數(shù)： | 11/20頁 |
| 文件大?。?/td> | 373K |
| 代理商： | K7A803609A |
K7A801809A
256Kx36 & 512Kx18 Synchronous SRAM
- 11 -
Rev 1.0
July 2000
K7A803609A
AC TIMING CHARACTERISTICS
(V
DD
=3.3V+0.165V/-0.165V, T
A
=0
°
C to +70
°
C)
Notes :
1. All address inputs must meet the specified setup and hold times for all rising clock edges whenever ADSC and/or ADSP is sampled low and
CS is sampled low. All other synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Both chip selects must be active whenever ADSC or ADSP is sampled low in order for the this device to remain enabled.
3. ADSC or ADSP must not be asserted for at least 2 Clock after leaving ZZ state.
PARAMETER
Symbol
-22
-20
-18
UNIT
Min
Max
MIN
MAX
Min
Max
Cycle Time
t
CYC
4.4
-
5.0
-
5.4
-
ns
Clock Access Time
t
CD
-
2.8
-
3.1
-
3.3
ns
Output Enable to Data Valid
t
OE
-
2.8
-
3.1
-
3.3
ns
Clock High to Output Low-Z
t
LZC
0
-
0
-
0
-
ns
Output Hold from Clock High
t
OH
1.0
-
1.0
-
1.0
-
ns
Output Enable Low to Output Low-Z
t
LZOE
0
-
0
-
0
-
ns
Output Enable High to Output High-Z
t
HZOE
-
2.8
-
3.0
-
3.0
ns
Clock High to Output High-Z
t
HZC
1.0
2.8
1.0
3.0
1.0
3.0
ns
Clock High Pulse Width
t
CH
1.8
-
2.0
-
2.4
-
ns
Clock Low Pulse Width
t
CL
1.8
-
2.0
-
2.4
-
ns
Address Setup to Clock High
t
AS
1.4
-
1.4
-
1.4
-
ns
Address Status Setup to Clock High
t
SS
1.4
-
1.4
-
1.4
-
ns
Data Setup to Clock High
t
DS
1.4
-
1.4
-
1.4
-
ns
Write Setup to Clock High (GW, BW, WE
X
)
t
WS
1.4
-
1.4
-
1.4
-
ns
Address Advance Setup to Clock High
t
ADVS
1.4
-
1.4
-
1.4
-
ns
Chip Select Setup to Clock High
t
CSS
1.4
-
1.4
-
1.4
-
ns
Address Hold from Clock High
t
AH
0.4
-
0.4
-
0.4
-
ns
Address Status Hold from Clock High
t
SH
0.4
-
0.4
-
0.4
-
ns
Data Hold from Clock High
t
DH
0.4
-
0.4
-
0.4
-
ns
Write Hold from Clock High (GW, BW, WE
X
)
t
WH
0.4
-
0.4
-
0.4
-
ns
Address Advance Hold from Clock High
t
ADVH
0.4
-
0.4
-
0.4
-
ns
Chip Select Hold from Clock High
t
CSH
0.4
-
0.4
-
0.4
-
ns
ZZ High to Power Down
t
PDS
2
-
2
-
2
-
cycle
ZZ Low to Power Up
t
PUS
2
-
2
-
2
-
cycle
Output Load(B),
(for t
LZC
, t
LZOE
, t
HZOE
& t
HZC
)
Dout
353
/
1538
5pF*
+3.3V for 3.3V I/O
/+2.5V for 2.5V I/O
319
/
1667
Fig. 1
* Including Scope and Jig Capacitance
Output Load(A)
Dout
Zo=50
RL=50
VL=1.5V for 3.3V I/O
V
DDQ
/2 for 2.5V I/O
30pF*
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