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參數(shù)資料
| 型號(hào)： | K7B321825M |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | Aluminum Snap-In Capacitor; Capacitance: 820uF; Voltage: 250V; Case Size: 22x50 mm; Packaging: Bulk |
| 中文描述： | 1Mx36 |
| 文件頁(yè)數(shù)： | 18/19頁(yè) |
| 文件大小： | 264K |
| 代理商： | K7B321825M |
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K7B321825M
1Mx36 & 2Mx18 Synchronous SRAM
- 18 -
Rev 2.0
Nov. 2003
K7B323625M
APPLICATION INFORMATION
DEPTH EXPANSION
The Samsung 2Mx18 Synchronous Burst SRAM has two additional chip selects for simple depth expansion.
This permits easy secondary cache upgrades from 2M depth to 4M depth without extra logic.
Data
Address
CLK
ADS
Microprocessor
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
2Mx18
SB
SRAM
(Bank 0)
CS
2
CS
2
CLK
ADSC
WEx
OE
CS
1
Address Data
ADV
ADSP
2Mx18
SB
SRAM
(Bank 1)
CLK
Address
Cache
Controller
A
[0:21]
A
[21]
A
[0:20]
A
[21]
A
[0:20]
I/O
[0:71]
CLOCK
ADSP
ADDRESS
[0:n]
Data Out
(Bank 0)
INTERLEAVE READ TIMING
(Refer to non-interleave write timing for interleave write timing)
(ADSP CONTROLLED , ADSC=HIGH)
Bank 0 is selected by CS
2
, and Bank 1 deselected by CS
2
Q1-1
Q1-2
Q1-4
Q1-3
OE
Data Out
(Bank 1)
t
SS
t
SH
A1
A2
WRITE
CS
1
A
n+1
ADV
Q2-1
Q2-2
Q2-4
Q2-3
t
AS
t
AH
t
CSS
t
CSH
t
WS
t
WH
t
ADVS
t
ADVH
t
OE
t
LZOE
t
HZC
Bank 0 is deselected by CS
2
, and Bank 1 selected by CS
2
Don
′
t Care
Undefined
t
CD
t
LZC
*Notes :
n = 14 32K depth , 15 64K depth
16 128K depth , 17 256K depth
18 512K depth , 19 1M depth
20 2M depth
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