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參數(shù)資料
| 型號： | K7I163682B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx36-bit, 1Mx18-bit DDRII CIO b2 SRAM |
| 中文描述： | 512Kx36位，1Mx18位首席信息官b2條DDRII的SRAM |
| 文件頁數(shù)： | 9/17頁 |
| 文件大?。?/td> | 378K |
| 代理商： | K7I163682B |
512Kx36 & 1Mx18 DDRII CIO b2 SRAM
- 9 -
Rev 3.1
July. 2004
K7I163682B
K7I161882B
ABSOLUTE MAXIMUM RATINGS*
*Note:
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. V
DDQ
must not exceed V
DD
during normal operation.
PARAMETER
SYMBOL
RATING
UNIT
Voltage on V
DD
Supply Relative to V
SS
V
DD
-0.5 to 2.9
V
Voltage on V
DDQ
Supply Relative to V
SS
V
DDQ
-0.5 to V
DD
V
Voltage on Input Pin Relative to V
SS
V
IN
-0.5 to V
DD+
0.3
V
Storage Temperature
T
STG
-65 to 150
°
C
°
C
°
C
Operating Temperature
T
OPR
0 to 70
Storage Temperature Range Under Bias
T
BIAS
-10 to 85
DC ELECTRICAL CHARACTERISTICS
(V
DD
=1.8V
±
0.1V, T
A
=0
°
C to +70
°
C)
Notes:
1. Minimum cycle. I
OUT
=0mA.
2. |I
OH
|=(V
DDQ
/2)/(RQ/5)
±
15% for 175
≤
RQ
≤
350
.
3. |I
OL
|=(V
DDQ
/2)/(RQ/5)
±
15% for 175
≤
RQ
≤
350
.
4. Minimum Impedance Mode when ZQ pin is connected to V
DDQ
.
5. Operating current is calculated with 50% read cycles and 50% write cycles.
6. Standby Current is only after all pending read and write burst opeactions are completed.
7. Programmable Impedance Mode.
8. These are DC test criteria. DC design criteria is V
REF
±
50mV. The AC V
IH
/V
IL
levels are defined separately for measuring
timing parameters.
9. V
IL
(Min)DC=
-
0.3V, V
IL
(Min)AC=-1.5V(pulse width
≤
3ns).
10. V
IH
(Max)DC=
V
DDQ
+0.3, V
IH
(Max)AC=
V
DDQ
+0.85V(pulse width
≤
3ns).
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
MAX
UNIT
NOTE
Input Leakage Current
I
IL
V
DD
=Max ; V
IN
=V
SS
to V
DDQ
-2
+2
μ
A
μ
A
Output Leakage Current
I
OL
Output Disabled,
-2
+2
Operating Current
(x36) : DDR
I
CC
V
DD
=Max , I
OUT
=0mA
Cycle Time
≥
t
KHKH
Min
-30
-
600
mA
1,5
-25
-
550
-20
-
500
-16
450
Operating Current
(x18) : DDR
I
CC
V
DD
=Max , I
OUT
=0mA
Cycle Time
≥
t
KHKH
Min
-30
-
500
mA
1,5
-25
-
450
-20
-
400
-16
350
Standby Current(NOP): DDR
I
SB1
Device deselected,
I
OUT
=0mA, f=Max,
All Inputs
≤
0.2V or
≥
V
DD
-0.2V
-30
-
260
mA
1,6
-25
-
240
-20
-
220
-16
-
200
Output High Voltage
V
OH1
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
2,7
Output Low Voltage
V
OL1
V
DDQ
/2-0.12
V
DDQ
/2+0.12
V
3,7
Output High Voltage
V
OH2
I
OH
=-1.0mA
V
DDQ
-0.2
V
DDQ
V
4
Output Low Voltage
V
OL2
I
OL
=1.0mA
V
SS
0.2
V
4
Input Low Voltage
V
IL
-0.3
V
REF
-0.1
V
8,9
Input High Voltage
V
IH
V
REF
+0.1
V
DDQ
+0.3
V
8,10
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