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參數(shù)資料
| 型號(hào)： | K7I643684M-FC20 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 72Mb DDRII SRAM Specification |
| 中文描述： | 72Mb SRAM的規(guī)范條DDRII |
| 文件頁(yè)數(shù)： | 6/18頁(yè) |
| 文件大小： | 424K |
| 代理商： | K7I643684M-FC20 |
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2Mx36 & 4Mx18 DDRII CIO b4 SRAM
K7I643684M
K7I641884M
- 6 -
Rev. 1.3 March 2007
The K7I643684M and K7I641884M are 75,497,472-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 2,097,152 words by 36bits for K7I643684M and 4,194,304 words by 18 bits for K7I641884M.
Address, data inputs, and all control signals are synchronized to the input clock (K or K).
Normally data outputs are synchronized to output clocks (C and C), but when C and C are tied high,
the data outputs are synchronized to the input clocks (K and K).
Read data are referenced to echo clock (CQ or CQ) outputs.
Read address and write address are registered on rising edges of the input K clocks.
Common address bus is used to access address both for read and write operations.
The internal burst counter is fixed to 4-bit sequential for both read and write operations.
Synchronous pipeline read and late write enable high speed operations.
Simple depth expansion is accomplished by using LD for port selection.
Byte write operation is supported with BW
0
and BW
1
(BW
2
and BW
3)
pins for x18 (x36) device.
IEEE 1149.1 serial boundary scan (JTAG) simplifies monitoring package pads attachment status with system.
The K7I643684M and K7I641884M are implemented with SAMSUNG's high performance 6T CMOS technology
and is available in 165pin FBGA packages. Multiple power and ground pins minimize ground bounce.
GENERAL DESCRIPTION
Read Operations
Read cycles are initiated by initiating R/W as high at the rising edge of the positive input clock K.
Address is presented and stored in the read address register synchronized with K clock.
For 4-bit burst DDR operation, it will access four 36-bit or 18-bit data words with each read command.
The first pipelined data is transferred out of the device triggered by C clock following next K clock rising edge.
Next burst data is triggered by the rising edge of following C clock rising edge.
Continuous read operations are initiated with K clock rising edge.
And pipelined data are transferred out of device on every rising edge of both C and C clocks.
In case C and C tied to high, output data are triggered by K and K instead of C and C.
When the LD is disabled after a read operation, the K7I643684M and K7I641884M will first complete
burst read operation before entering into deselect mode at the next K clock rising edge.
Then output drivers disabled automatically to high impedance state.
Single Clock Mode
K7I643684M and K7I641884M can be operated with the single clock pair K and K, instead of C or C for output clocks.
To operate these devices in single clock mode, C and C must be tied high during power up
and must be maintained high during operation.
After power up, this device can
′
t change to or from single clock mode.
System flight time and clock skew could not be compensated in this mode.
Write cycles are initiated by activating R/W as low at the rising edge of the positive input clock K.
Address is presented and stored in the write address register synchronized with next K clock.
For 4-bit burst DDR operation, it will write two 36-bit or 18-bit data words with each write command.
The first "late writed" data is transferred and registered in to the device synchronous with next K clock rising edge.
Next burst data is transferred and registered synchronous with following K clock rising edge.
Continuous write operations are initiated with K rising edge.
And “l(fā)ate writed” data is presented to the device on every rising edge of both K and K clocks.
When the LD is disabled, the K7I643684M and K7I641884M will enter into deselect mode.
The device disregards input data presented on the same cycle W disabled.
The K7I643684M and K7I641884M support byte write operations.
With activating BW
0
or BW
1
(BW
2
or BW
3)
in write cycle, only one byte of input data is presented.
In K7I641884M, BW
0
controls write operation to D0:D8, BW
1
controls write operation to D9:D17.
And in K7I643684M BW
2
controls write operation to D18:D26, BW
3
controls write operation to D27:D35.
Write Operations
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| K7I643684M-FC25 | 72Mb DDRII SRAM Specification |
| K7I643684M-FC30 | 72Mb DDRII SRAM Specification |
| K7I643684M-FCI16 | 72Mb DDRII SRAM Specification |
| K7I643684M-FECI25 | 72Mb DDRII SRAM Specification |
| K7I643684M-FECI30 | 72Mb DDRII SRAM Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| K7I643684M-FC25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FC30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FCI16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FCI20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FECI25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
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