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參數(shù)資料
| 型號： | K7I643684M-FECI25 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 72Mb DDRII SRAM Specification |
| 中文描述： | 72Mb SRAM的規(guī)范條DDRII |
| 文件頁數(shù)： | 4/18頁 |
| 文件大小： | 424K |
| 代理商： | K7I643684M-FECI25 |
2Mx36 & 4Mx18 DDRII CIO b4 SRAM
K7I643684M
K7I641884M
- 4 -
Rev. 1.3 March 2007
PIN CONFIGURATIONS
(TOP VIEW)
K7I643684M(1Mx36)
Notes:
1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
2. BW
0
controls write to DQ0:DQ8, BW
1
controls write to DQ9:DQ17, BW
2
controls write to DQ18:DQ26 and BW
3
controls write to DQ27:DQ35.
1
2
3
4
5
6
K
K
7
8
9
10
SA
NC
DQ17
NC
DQ15
NC
NC
V
REF
DQ13
DQ12
NC
DQ11
NC
DQ9
TMS
11
CQ
DQ8
DQ7
DQ16
DQ6
DQ5
DQ14
ZQ
DQ4
DQ3
DQ2
DQ1
DQ10
DQ0
TDI
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
CQ
NC
NC
NC
NC
NC
NC
Doff
NC
NC
NC
NC
NC
NC
TDO
NC
/
SA*
DQ27
NC
DQ29
NC
DQ30
DQ31
V
REF
NC
NC
DQ33
NC
DQ35
NC
TCK
SA
DQ18
DQ28
DQ19
DQ20
DQ21
DQ22
V
DDQ
DQ32
DQ23
DQ24
DQ34
DQ25
DQ26
SA
R/W
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
BW
2
BW
3
SA
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
BW
1
BW
0
SA1
V
SS
V
SS
V
DD
V
DD
V
DD
V
DD
V
DD
V
SS
V
SS
SA
SA
SA
LD
SA
V
SS
V
SS
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
SS
V
SS
SA
SA
SA
NC
NC
NC
NC
NC
NC
V
DDQ
NC
NC
NC
NC
NC
NC
SA
SA0
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
V
SS
SA
C
C
PIN NAME
Notes:
1. C, C, K or K cannot be set to V
REF
voltage.
2. When ZQ pin is directly connected to V
DD
output impedance is set to minimum value
and it
cannot be connected to ground or left unconnected
.
3. Not connected to chip pad internally.
SYMBOL
K, K
C, C
CQ, CQ
Doff
SA0,SA1
SA
PIN NUMBERS
6B, 6A
6P, 6R
11A, 1A
1H
6C,7C
DESCRIPTION
Input Clock
Input Clock for Output Data
Output Echo Clock
DLL Disable when low
Burst Count Address Inputs
Address Inputs
NOTE
1
3A,9A,10A,4B,8B,5C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
2B,3B,11B,3C,10C,11C,2D,3D,11D,3E,10E,11E,2F,3F
11F,2G,3G,11G,3J,10J,11J,3K,10K,11K,2L,3L,11L
3M,10M,11M,2N,3N,11N,3P,10P,11P
DQ0-35
Data Inputs Outputs
R/W
4A
Read, Write Control Pin, Read active
when high
LD
8A
Synchronous Load Pin, bus Cycle
sequence is to be defined when low
BW
0
, BW
1,
BW
2
, BW
3
V
REF
ZQ
V
DD
V
DDQ
7B,7A,5A,5B
2H,10H
11H
Block Write Control Pin,active when low
Input Reference Voltage
Output Driver Impedance Control Input
Power Supply (1.8 V)
Output Power Supply (1.5V or 1.8V)
2
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,
4M-8M,4N,8N
V
SS
Ground
TMS
TDI
TCK
TDO
10R
11R
2R
1R
JTAG Test Mode Select
JTAG Test Data Input
JTAG Test Clock
JTAG Test Data Output
NC
2A,1B,9B,10B,1C,2C,9C,1D,9D,10D,1E,2E,9E,
1F,9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K
1L,9L,10L,1M,2M,9M,1N,9N,10N,1P,2P,9P
No Connect
3
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| K7I643684M-FECI30 | 72Mb DDRII SRAM Specification |
| K7I643684M-FI16 | 72Mb DDRII SRAM Specification |
| K7I643684M-FI20 | 72Mb DDRII SRAM Specification |
| K7I643684M-FI25 | 72Mb DDRII SRAM Specification |
| K7I643684M-FI30 | 72Mb DDRII SRAM Specification |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| K7I643684M-FECI30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FI16 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FI20 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FI25 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
| K7I643684M-FI30 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:72Mb DDRII SRAM Specification |
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