參數(shù)資料
型號(hào)： K9K2G16Q0M-P
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： ULTRA2 LVD SCSI INTERNAL CBL 3
中文描述： 256M × 8位/ 128M的× 16位NAND閃存
文件頁(yè)數(shù)： 32/38頁(yè)
文件大?。?/td> 734K
代理商： K9K2G16Q0M-P
FLASH MEMORY
32
K9K2G08Q0M-YCB0,YIB0,PCB0,PIB0
K9K2G08U0M-YCB0,YIB0,PCB0,PIB0
K9K2G16Q0M-YCB0,YIB0,PCB0,PIB0
K9K2G16U0M-YCB0,YIB0,PCB0,PIB0
K9K2G08U0M-VCB0,VIB0,FCB0,FIB0
Cache Program
Cache Program is an extension of Page Program, which is executed with 2112byte(X8 device) or 1056word(X16 device) data regis-
ters, and is available only within a block. Since the device has 1 page of cache memory, serial data input may be executed while data
stored in data register are programmed into memory cell.
Figure 9. Random Data Input In a Page
80h
R/B
Address & Data Input
I/O
0
Pass
10h
70h
Fail
t
PROG
85h
Address & Data Input
After writing the first set of data up to 2112byte(X8 device) or 1056word(X16 device) into the selected cache registers, Cache Pro-
gram command (15h) instead of actual Page Program (10h) is inputted to make cache registers free and to start internal program
operation. To transfer data from cache registers to data registers, the device remains in Busy state for a short period of time(tCBSY)
and has its cache registers ready for the next data-input while the internal programming gets started with the data loaded into data
registers. Read Status command (70h) may be issued to find out when cache registers become ready by polling the Cache-Busy sta-
tus bit(I/O 6). Pass/fail status of only the previouse page is available upon the return to Ready state. When the next set of data is
inputted with the Cache Program command, tCBSY is affected by the progress of pending internal programming. The programming of
the cache registers is initiated only when the pending program cycle is finished and the data registers are available for the transfer of
data from cache registers. The status bit(I/O5) for internal Ready/Busy may be polled to identify the completion of internal program-
ming. If the system monitors the progress of programming only with R/B, the last page of the target programming sequence must be
progammed with actual Page Program command (10h). If the Cache Program command (15h) is used instead, status bit (I/O5) must
be polled to find out when the last programming is actually finished before starting other operations such as read. Pass/fail status is
available in two steps. I/O 1 returns with the status of the previous page upon Ready or I/O6 status bit changing to "1", and later I/O
0 with the status of current page upon true Ready (returning from internal programming) or I/O 5 status bit changing to "1". I/O 1 may
be read together when I/O 0 is checked.
Figure 10. Cache Program
(available only within a block)
t
CBSY
80h
R/B
80h
Address &
Data Input
15h
80h
Address &
Data Input
15h
80h
Address &
Data Input
10h
t
CBSY
t
CBSY
t
PROG
70h
Address &
Data Input*
15h
80h
R/B
70h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
Status
80h
70h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
Status
80h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
80h
t
CBSY
Address &
Data Input
Col Add1,2 & Row Add1,2,3
Data
15h
70h
output
70h
Status
output
Check I/O5 for internal ready/busy
Check I/O0,1 for pass/fail
Check I/O1 for pass/fail
I/Ox
I/Ox
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
Col Add1,2 & Row Add1,2,3
Data
"0"
"1"
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
K9K2G16Q0M-PCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G16Q0M-PIB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G16Q0M-Y 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G16Q0M-YCB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
K9K2G16Q0M-YIB0 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:256M x 8 Bit / 128M x 16 Bit NAND Flash Memory
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