- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄9980 > KAD5512P-12Q48 (Intersil)IC ADC 12BIT 125MSPS SGL 48-QFN PDF資料下載
參數(shù)資料
| 型號(hào)： | KAD5512P-12Q48 |
| 廠商： | Intersil |
| 文件頁(yè)數(shù)： | 19/36頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 125MSPS SGL 48-QFN |
| 產(chǎn)品培訓(xùn)模塊： | High-Speed Analog-to-Digital Converters |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | FemtoCharge™ |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 125M |
| 數(shù)據(jù)接口： | 串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 235mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤(pán) |
| 供應(yīng)商設(shè)備封裝： | 48-QFN（7x7） |
| 包裝： | 托盤(pán) |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)差分，單極 |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)當(dāng)前第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)
KAD5512P
26
FN6807.4
October 1, 2010
ADDRESS 0X25: MODES
Two distinct reduced power modes can be selected. By
default, the tri-level NAPSLP pin can select normal
operation or sleep modes (refer to “Nap/Sleep” on
page 21). This functionality can be overridden and
controlled through the SPI. This is an indexed function
when controlled from the SPI, but a global function when
driven from the pin. This register is not changed by a
Soft Reset.
Nap mode must be entered by executing the following
sequence:
Return to Normal operation as follows:
Global Device Configuration/Control
ADDRESS 0X71: PHASE_SLIP
When using the clock divider, it’s not possible to
determine the synchronization of the incoming and
divided clock phases. This is particularly important when
multiple ADCs are used in a time-interleaved system.
The phase slip feature allows the rising edge of the
divided clock to be advanced by one input clock cycle
when in CLK/4 mode, as shown in Figure 41. Execution
of a phase_slip command is accomplished by first writing
a ‘0’ to bit 0 at address 71h followed by writing a ‘1’ to bit
0 at address 71h (32 sclk cycles).
ADDRESS 0X72: CLOCK_DIVIDE
The KAD5512P has a selectable clock divider that can be
set to divide by four, two or one (no division). By default,
the tri-level CLKDIV pin selects the divisor (refer to “VCM
Output” on page 20). This functionality can be
overridden and controlled through the SPI, as shown in
Table 11. This register is not changed by a Soft Reset.
ADDRESS 0X73: OUTPUT_MODE_A
The output_mode_A register controls the physical output
format of the data, as well as the logical coding. The
KAD5512P can present output data in two physical
formats: LVDS or LVCMOS. Additionally, the drive
strength in LVDS mode can be set high (3mA) or low
(2mA). By default, the tri-level OUTMODE pin selects the
mode and drive level (refer to “Digital Outputs” on
page 21). This functionality can be overridden and
controlled through the SPI, as shown in Table 12.
Data can be coded in three possible formats: two’s
complement, Gray code or offset binary. By default, the
tri-level OUTFMT pin selects the data format (refer to “Data
Format” on page 22). This functionality can be overridden
and controlled through the SPI, as shown in Table 13.
This register is not changed by a Soft Reset.
TABLE 10. POWER-DOWN CONTROL
VALUE
0x25[2:0]
POWER-DOWN MODE
000
Pin Control
001
Normal Operation
010
Nap Mode
100
Sleep Mode
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
2
0x25
0x02
3
0x10
0x02
4
0x25
0x02
SEQUENCE
REGISTER
VALUE
1
0x10
0x01
2
0x25
0x01
3
0x10
0x02
4
0x25
0x01
TABLE 11. CLOCK DIVIDER SELECTION
VALUE
0x72[2:0]
CLOCK DIVIDER
000
Pin Control
001
Divide by 1
010
Divide by 2
100
Divide by 4
TABLE 12. OUTPUT MODE CONTROL
VALUE
0x93[7:5]
000
Pin Control
001
LVDS 2mA
010
LVDS 3mA
100
LVCMOS
FIGURE 41. PHASE SLIP: CLK÷4 MODE, fCLOCK =
1000MHz
CLK
CLK÷4
SLIP ONCE
CLK = CLKP – CLKN
CLK÷4
SLIP TWICE
1.00ns
4.00ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IDT72V3641L20PF | IC SYNCFIFO 1024X36 20NS 120TQFP |
| D38999/26WA98PD | CONN PLUG 3POS STRAIGHT W/PINS |
| MS27468T21A41S | CONN RCPT 41POS JAM NUT W/SCKT |
| MS27467T9B35S EDR | CONN PLUG 6POS STRAIGHT W/SCKT |
| D38999/20WF32SA | CONN RCPT 32POS WALL MNT W/SCKT |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KAD5512P-12Q72 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 125MSPS SINGL ADC PROG LVDS/LVCMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| KAD5512P-17Q48 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 170MSPS SINGL ADC PROG LVDS/LVCMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| KAD5512P-17Q72 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 170MSPS SINGL ADC PROG LVDS/LVCMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| KAD5512P-21Q48 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 210MSPS SINGL ADC PROG LVDS/LVCMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| KAD5512P-21Q72 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-BIT 210MSPS SINGL ADC PROG LVDS/LVCMOS RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。