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參數(shù)資料
| 型號： | KESRX01 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | 290 - 460MHz ASK Receiver |
| 中文描述： | 290 - 460MHz ASK接收機 |
| 文件頁數(shù)： | 3/11頁 |
| 文件大?。?/td> | 185K |
| 代理商： | KESRX01 |
3
KESRX01
Pin
13
14
15
16
17
18
19
20
21
22
23
24
Symbol
VEE
PD
VCO1
VCO2
NC
NC
LF
DF0
DF1
DF2
XTAL1
XTAL2
Description
Negative power supply (0V)
PLL power down
VCO maintaining amplifer
VCO maintaining amplifier
Not connected, unless to GND
Not connected,unless to GND
PLL loop filter O/P output
Data filter – external connection
Data filter – external connection
Data filter – external connection
Crystal oscillator
Crystal oscillator
PIN LISTING
Pin
1
2
3
4
5
6
7
8
9
10
Symbol
IFDC1
IFDC2
IF1
IF2
VCC
MIXIP
RFOP
VEERF
RFIN
DSN
Description
IF amplifier – decouple point
IF amplifer – decouple point
Mixer output
IF amplifer input
Positive power supply
RF mixer input (tank)
RF amplifier output (tank)
RF amplifier ground
RF input (antenna)
Bit slicer comparator
negative input
Bit slicer comparator output
Peak detector output
11
12
DATAOP
PEAK
FUNCTION
Phase locked loop
The phase locked loop generates the local oscillator by
frequency multiplication of a crystal referenced oscillator.
Dividers
A divide by 64 prescaler is present in the PLL feedback
loop. The local oscillator frequency is then Fo=64xF
ref
. A
system operating at 433.92MHz (RFIN) with a 270KHz IF
frequency would require a reference of 6.77578MHz
(assuming mixer low side injection). Alternative choice of
crystal and tank components permit operation at specific
frequencies in the range 290 – 460MHz.
Phase detector
The phase detector used is a phase frequency detector
(PFD) with a current (charge pump) output.
DP
DPb
VCO1
VCO2
Fig. 3 Input circuit of VCO and divider chain
This phase detector has a triangle characteristic for an
input phase error in the range -2
π
<
θ<
+2
π
and has the benefit
of being a true frequency detector (as well as a phase
detector) and hence will always achieve lock for any initial
VCO frequency.
The charge pump provides an output current in the range
±
30
μ
A and hence gives a phase detector gain of 4.8
μ
A/rad.
The PLL loop characteristics such as lock-up time, capture
range, loop bandwidth and VCO reference sideband
suppression are controlled by the external loop filter.
For the intended application a 2nd order loop should be
sufficient as shown in the test circuit Fig. 6.
VCO
A balanced configuration is used with the LC tank
connected externally across VCO1 and VCO2 Fig. 3.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KESRX04QP1S | 260 to 470MHz. ASK Receiver with Power Down |
| KESRX04QP1T | 260 to 470MHz. ASK Receiver with Power Down |
| KESRX04 | 260 to 470MHz. ASK Receiver with Power Down |
| KESRX04IG | 260 to 470MHz. ASK Receiver with Power Down |
| KESRX05 | 260 to 470MHz ASK Receiver with Power Down |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KESRX01/IG/QP1S | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:290 - 460MHz ASK Receiver |
| KESRX01/IG/QP1T | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:290 - 460MHz ASK Receiver |
| KESRX01G/IG/QP2Q | 制造商:Rochester Electronics LLC 功能描述: 制造商:Zarlink Semiconductor Inc 功能描述: 制造商:ZARLINK 功能描述: |
| KESRX01G/IG/QP2S | 制造商:Microsemi Corporation 功能描述: |
| KESRX04 | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:260 to 470MHz. ASK Receiver with Power Down |
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