參數(shù)資料
型號(hào)： KFH1G16D2M-DED
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： FLASH MEMORY
中文描述： 閃存
文件頁數(shù)： 49/93頁
文件大?。?/td> 1219K
代理商： KFH1G16D2M-DED
OneNAND512/OneNAND1GDDP
FLASH MEMORY
49
Load Operation
The load operation is initiated by setting up the start address from which the data is to be loaded. The load command is issued in
order to initiate the load. The device transfers the data from NAND Flash array into the BufferRAM. The ECC is checked and any
detected and corrected error is reported in the status response as well as any unrecoverable error. When the BufferRAM has been
filled an interrupt is issued to the host in order to read the contents of the BufferRAM. The read from the BufferRAM consist of asyn-
chronous read mode or synchronous read mode. The status information related to the BufferRAM fill operation can be checked by
the host if required.
The device provides dual data buffer memory architecture. The device is capable of data-read operation from one data buffer and
data-load operation to the other data buffer simultaneously. Refer to the information for more details in "Read while Load operation".
Start
Write ’DFS*, FBA’ of Flash
Add: F100h DQ=FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
Select DataRAM for DDP
Add: F101h DQ=DBS
Write ’Load’ Command
Add: F220h
DQ=0000h or 0013h
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Figure 11. Load operation flow-chart
* DBS, DFS is for DDP
Host reads data from
DataRAM
Read completed
Write 0 to interrupt register
Add: F241h DQ=0000h
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