參數(shù)資料
型號: KFH1G16U2M-DIB5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: FLASH MEMORY(54MHz)
中文描述: 閃存(54MHz之間)
文件頁數(shù): 78/125頁
文件大小: 1657K
代理商: KFH1G16U2M-DIB5
OneNAND1G(KFG1G16Q2M-DEB5)
FLASH MEMORY
78
OneNAND2G(KFH2G16Q2M-DEB5)
OneNAND4G(KFW4G16Q2M-DEB5)
Program Operation Flow Diagram
During the execution of the Internal Program Routine, the host is not required to provide any further controls or
timings. Furthermore, all commands, except a Reset command, will be ignored. A reset during a program operation will cause data
corruption at the corresponding location.
If a program error is detected at the completion of the Internal Program Routine, map out the block, including the page in error, and
copy the target data to another block. An error is signaled if DQ10 = "1" of Controller Status Register(F240h) .
Data input from the Host to the DataRAM can be done at any time during the Internal Program Routine after "Start" but before the
"Write Program Command" is written.
Start
Data Input
Completed
Write ’DFS*, FBA’ of Flash
Add: F100h DQ=DFS, FBA
Write ’FPA, FSA’ of Flash
Add: F107h DQ=FPA, FSA
Select DataRAM for DDP
1)
Add: F101h DQ=DBS*
Write Data into DataRAM
2)
ADD: DP DQ=Data-in
Program completed
Write ’Program’ Command
Add: F220h
DQ=0080h or 001Ah
Wait for INT register
low to high transition
Add: F241h DQ[15]=INT
Read Controller
Status Register
Add: F240h DQ[10]=Error
DQ[10]=0
Program Error
YES
NO
NO
YES
* DBS, DFS is for DDP
: If program operation results in an error, map out
the block including the page in error and copy the
target data to another block.
*
Note 1) This must happen before data input
2) Data input could be done anywhere between "Start" and "Write Program Command".
Write 0 to interrupt register
Add: F241h DQ=0000h
Write ’BSA, BSC’ of DataRAM
Add: F200h DQ=BSA, BSC
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