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參數(shù)資料
| 型號： | KM23C4100DG |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M-Bit (512Kx8 /256Kx16) CMOS Mask ROM(4M位 (512Kx8 /256Kx16) CMOS掩膜ROM) |
| 中文描述： | 4分位（512Kx8 / 256Kx16）的CMOS掩模ROM（4分位（512Kx8 / 256Kx16）的CMOS掩膜光盤） |
| 文件頁數(shù)： | 3/4頁 |
| 文件大小： | 78K |
| 代理商： | KM23C4100DG |
KM23C4100D(G)
CMOS MASK ROM
TEST CONDITIONS
Item
Value
Input Pulse Levels
0.6V to 2.4V
Input Rise and Fall Times
10ns
Input and Output timing Levels
0.8V and 2.0V
Output Loads
1 TTL Gate and C
L
=100pF
AC CHARACTERISTICS
(T
A
=0
°
C to +70
°
C, V
CC
=5V
±
10%, unless otherwise noted.)
READ CYCLE
Item
Symbol
KM23C4100D(G)-8
KM23C4100D(G)-10
KM23C4100D(G)-12
Unit
Min
Max
Min
Max
Min
Max
Read Cycle Time
t
RC
80
100
120
ns
Chip Enable Access Time
t
ACE
80
100
120
ns
Address Access Time
t
AA
80
100
120
ns
Output Enable Access Time
t
OE
40
50
60
ns
Output or Chip Disable to
Output High-Z
t
DF
20
20
20
ns
Output Hold from Address Change
t
OH
0
0
0
ns
TIMING DIAGRAM
READ
ADD1
ADD2
VALID DATA
VALID DATA
t
OH
t
DF(*3)
ADD
A
0
~A
17
A
-1(*1)
CE
OE
D
OUT
D
0
~D
7
D
8
~D
15(*2)
t
RC
t
ACE
t
OE
t
AA
NOTES :
*1. Byte Mode only. A
-1
is Least Significant Bit Address.(BHE = V
IL
)
*2. Word Mode only.(BHE = V
IH
)
*3. t
DF
is defined as the time at which the outputs achieve the open circuit condition and is not referenced to V
OH
or V
OL
level.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM23C4100DT | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M-Bit (512Kx8 /256Kx16) CMOS MASK ROM |
| KM23C64000T | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM |
| KM-23CGCK-F | 制造商:Kingbright Corporation 功能描述: |
| KM-23EC | 制造商:KINGBRIGHT 制造商全稱:Kingbright Corporation 功能描述:SOT-23 SURFACE MOUNT LED LAMP |
| KM-23EC-F | 制造商:Kingbright Corporation 功能描述: |
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