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參數(shù)資料
| 型號： | KM416V10CJ-L5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| 中文描述： | 100萬× 16的CMOS動態(tài)隨機存儲器的擴展數(shù)據(jù)輸出 |
| 文件頁數(shù)： | 7/35頁 |
| 文件大?。?/td> | 494K |
| 代理商： | KM416V10CJ-L5 |
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KM416C1004C, KM416C1204C
KM416V1004C, KM416V1204C
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles
before proper device operation is achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
Assumes that t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min), then the cycle is a read-
modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions
is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
KM416C/V10(2)04C/C-L Truth Table
RAS
LCAS
UCAS
W
OE
DQ0 - DQ7
DQ8-DQ15
STATE
H
X
X
X
X
Hi-Z
Hi-Z
Standby
L
H
H
X
X
Hi-Z
Hi-Z
Refresh
L
L
H
H
L
DQ-OUT
Hi-Z
Byte Read
L
H
L
H
L
Hi-Z
DQ-OUT
Byte Read
L
L
L
H
L
DQ-OUT
DQ-OUT
Word Read
L
L
H
L
H
DQ-IN
-
Byte Write
L
H
L
L
H
-
DQ-IN
Byte Write
L
L
L
L
H
DQ-IN
DQ-IN
Word Write
L
L
L
H
H
Hi-Z
Hi-Z
-
8.
6.
5.
10.
9.
3.
2.
1.
4.
7.
相關(guān)PDF資料 |
PDF描述 |
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| KM416V10CJ-L6 | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V10CT-L45 | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V10CT-L5 | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V10CT-L6 | 1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM416V10CJ-L6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V10CT-L45 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V10CT-L5 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V10CT-L6 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:1M x 16Bit CMOS Dynamic RAM with Extended Data Out |
| KM416V1200ATL6TQ | 制造商:SAMSUNG 功能描述:* |
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