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參數(shù)資料
| 型號： | KM44C4005C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out(4M x 4位 CMOS 四CAS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| 中文描述： | 4米× 4位的CMOS DRAM與中科院四擴(kuò)展數(shù)據(jù)輸出（4米× 4位的CMOS四中科院動(dòng)態(tài)隨機(jī)存儲器（帶擴(kuò)展數(shù)據(jù)輸出）） |
| 文件頁數(shù)： | 1/20頁 |
| 文件大?。?/td> | 363K |
| 代理商： | KM44C4005C |
CMOS DRAM
KM44C4005C, KM44C4105C
This is a family of 4,194,304 x 4 bit Quad CAS with Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high
speed random access of memory cells within the same row, so called Hyper Page Mode. Refresh cycle (2K Ref. or 4K Ref.), access
time (-5 or -6), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of
this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is avail-
able in L-version. Four separate CAS pins provide for seperate I/O operation allowing this device to operate in parity mode.
This 4Mx4 Extended Data Out Quad CAS DRAM family is fabricated using Samsung
′
s advanced CMOS process to realize high band-
width, low power consumption and high reliability.
Part Identification
- KM44C4005C/C-L (5V, 4K Ref.)
- KM44C4105C/C-L (5V, 2K Ref.)
Extended Data Out mode operation
(Fast Page Mode with Extended Data Out)
Four separate CAS pins provide for separate I/O operation
CAS-before-RAS refresh capability
RAS-only and Hidden refresh capability
Self-refresh capability (L-ver only)
Fast parallel test mode capability
TTL compatible inputs and outputs
Early Write or output enable controlled write
JEDEC Standard pinout
Available in Plastic SOJ and TSOP(II) packages
Single +5V
±
10% power supply
Control
Clocks
RAS
CAS0 - 3
W
Vcc
Vss
DQ0
to
DQ3
A0-A11
(A0 - A10)
*1
A0 - A9
(A0 - A10)
*1
Memory Array
4,194,304 x 4
Cells
SAMSUNG ELECTRONICS CO., LTD.
reserves the right to
change products and specifications without notice.
4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles
Part
NO.
Refresh
cycle
Refresh period
Normal
64ms
32ms
L-ver
C4005C
C4105C
4K
2K
128ms
Performance Range
Speed
t
RAC
-5
50ns
-6
60ns
t
CAC
13ns
15ns
t
RC
84ns
104ns
t
HPC
20ns
25ns
Active Power Dissipation
Speed
Refresh Cycle
4K
495
440
2K
605
550
-5
-6
Unit : mW
S
Data out
Buffer
Data in
Buffer
OE
Note)
*1
: 2K Refresh
Col. Address Buffer
Row Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
Column Decoder
Row Decoder
VBB Generator
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| KM44C4105C | 4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out(4M x 4位 CMOS 四CAS 動(dòng)態(tài)RAM(帶擴(kuò)展數(shù)據(jù)輸出)) |
| KM44C4103C | 4M x 4Bit CMOS Quad CAS DRAM with Fast Page Mode(4M x 4位CMOS四CAS 動(dòng)態(tài)RAM(帶快速頁模式)) |
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| KM44C4103CK-6 | 制造商:Samsung Semiconductor 功能描述:DRAM Chip FPM 16M-Bit 4Mx4 5V 28-Pin SOJ |
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| KM44C4105C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 4Bit CMOS Quad CAS DRAM with Extended Data Out |
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