參數(shù)資料
型號(hào)： KM48L16031BT-G(L)Y
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Specification Version 1.0
中文描述： DDR SDRAM的規(guī)范版本1.0
文件頁(yè)數(shù)： 19/53頁(yè)
文件大小： 669K
代理商： KM48L16031BT-G(L)Y
- 19 -
REV. 1.0 November. 2. 2000
128Mb DDR SDRAM
3.2.5 Row Active
The Bank Activation command is issued by holding CAS and WE high with CS and RAS low at the rising
edge of the clock(CK). The DDR SDRAM has four independent banks, so two Bank Select addresses(BA0,
BA1) are required. The Bank Activation command must be applied before any Read or Write operation is exe-
cuted. The delay from the Bank Activation command to the first read or write command must meet or exceed
the minimum of RAS to CAS delay time(tRCD min). Once a bank has been activated, it must be precharged
before another Bank Activation command can be applied to the same bank. The minimum time interval
between interleaved Bank Activation commands(Bank A to Bank B and vice versa) is the Bank to Bank delay
time(tRRD min).
Address
Command
RAS-CAS delay(
t
RCD
)
Bank A
Bank Activation Command Cycle
(CAS Latency = 2)
Bank A
Row Addr.
Bank A
Col. Addr.
Write A
Precharge
NOP
RAS-RAS delay time(
t
RRD
)
Bank B
Row Addr.
Bank A
Row. Addr.
Bank B
Bank A
NOP
ROW Cycle Time(
t
RC
)
Tn
Tn+1
Tn+2
2
0
1
: Don
′
t care
CK
CK
3.2.6 Read Bank
3.2.7 Write Bank
This command is used after the row activate command to initiate the burst read of data. The read command
is initiated by activating RAS, CS, CAS, and deasserting WE at the same clock sampling(rising) edge as
described in the command truth table. The length of the burst and the CAS latency time will be determined by
the values programmed during the MRS command.
This command is used after the row activate command to initiate the burst write of data. The write com-
mand is initiated by activating RAS, CS, CAS, and WE at the same clock sampling(rising) edge as described in
the command truth table. The length of the burst will be determined by the values programmed during the
MRS command.
Figure 8. Bank activation command cycle timing
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