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參數(shù)資料
| 型號(hào)： | KM48S8030C |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 8Bit x 4 Banks Synchronous DRAM |
| 中文描述： | 200萬(wàn)× 8位× 4銀行同步DRAM |
| 文件頁(yè)數(shù)： | 7/8頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | KM48S8030C |
KM48S8030C
PC133 CMOS SDRAM
REV. 0 Oct. '98
Preliminary
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
Symbol
-A
Unit
Note
Min
Max
CLK cycle time
CAS latency=3
t
CC
7.5
1000
ns
1
-
-
CLK to valid
output delay
CAS latency=3
t
SAC
5.4
ns
1,2
-
-
Output data
hold time
CAS latency=3
t
OH
2.7
ns
2
-
-
CLK high pulse width
t
CH
2.5
ns
3
CLK low pulse width
t
CL
2.5
ns
3
Input setup time
t
SS
1.5
ns
3
Input hold time
t
SH
0.8
ns
3
CLK to output in Low-Z
t
SLZ
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
t
SHZ
5.4
ns
-
-
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Notes :
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|---|---|
| KM48S8030CT-G/FA | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit x 4 Banks Synchronous DRAM |
| KM48S8030D | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| KM48V2000B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48V2100B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48V2104CS-L6 | 制造商:Samsung Semiconductor 功能描述: |
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