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參數(shù)資料
| 型號： | KM48S8030D |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64Mbit SDRAM 2M x 8Bit x 4 Banks Synchronous DRAM LVTTL |
| 中文描述： | 64Mbit SDRAM的200萬× 8位× 4銀行同步DRAM LVTTL |
| 文件頁數(shù)： | 2/11頁 |
| 文件大小： | 117K |
| 代理商： | KM48S8030D |
KM48S8030D
CMOS SDRAM
Rev. 0.0 May 1999
Revision History
Revision 0.0 (May 15, 1999)
Changed tRDL from 1CLK to 2CLK in OPERATING AC PARAMETER.
Skip ICC4 value of CL=2 in DC characteristics in datasheet.
Define a new parameter of tDAL( 2CLK +20ns), Last data in to Active delay in OPERATING AC PARAMETER.
Eliminated FREQUENCY vs.PARAMETER RELATIONSHIP TABLE.
Symbol Change Notice
Before
After
I
IL
I
IL
I
OL
Input leakage current (inputs)
Input leakage current (I/O pins)
Output open @ DC characteristic table
I
LI
Input leakage current
I
o
Output open @ DC characteristic table
Test Condition in
DC CHARACTERISTIC Change Notice
Symbol
Before
After
I
CC2P ,
I
CC3P
CKE
≤
V
IL
(max), t
CC
= 15ns
CKE
≤
V
IL
(max), t
CC
= 10ns
I
CC2N ,
I
CC3N
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 15ns
Input signals are changed one time during 30ns
CKE
≥
V
IH
(min), CS
≥
V
IH
(min), t
CC
= 10ns
Input signals are changed one time during 20ns
I
CC4
2 Banks activated
4 Banks activated
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