- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373157 > KM48V2000B (SAMSUNG SEMICONDUCTOR CO. LTD.) 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode PDF資料下載
參數(shù)資料
| 型號(hào)： | KM48V2000B |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| 中文描述： | 200萬× 8位的CMOS動(dòng)態(tài)隨機(jī)存儲(chǔ)器的快速頁面模式 |
| 文件頁數(shù)： | 8/8頁 |
| 文件大?。?/td> | 79K |
| 代理商： | KM48V2000B |
KM48C2000B, KM48C2100B
KM48V2000B, KM48V2100B
CMOS DRAM
NOTES
An initial pause of 200us is required after power-up followed by any 8 ROR or CBR cycles before proper device operation is
achieved.
V
IH
(min) and V
IL
(max) are reference levels for measuring timing of input signals.
Transition times are measured between V
IH
(min) and V
IL
(max) and are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max) can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then access time is controlled exclusively by
t
CAC
.
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to V
oh
or V
ol
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If
t
WCS
t
WCS
(min), the cycles is an early write cycle and the data output will remain high impedance for
the duration of the cycle. If
t
CWD
t
CWD
(min),
t
RWD
t
RWD
(min),
t
AWD
t
AWD
(min) and
t
CPWD
t
CPWD
(min), then the cycle is a
read-modify-write cycle and the data output will contain the data read from the selected address. If neither of the above condi-
tions is satisfied, the condition of the data out is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS falling edge in ealy write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max) can be met.
t
RAD
(max) is specified as a reference point only.
If
t
RAD
is greater than the specified
t
RAD
(max) limit, then access time is controlled by
t
AA
.
These specifications are applied in the test mode.
In test mode read cycle, the values of
t
RAC,
t
AA
and
t
CAC
are delayed by 2ns to 5ns for the specified values. These parame-
ters should be specified in test mode cycles by adding 5ns to the specified value in this data sheet.
For all of the refresh modes except for distributed CAS -before- RAS refresh, 4096(4K Ref.)/2048(2K Ref.) cycles of burst
refresh must be executed within 16ms before and after self-refresh in order to meet refresh specification.
7.
6.
5.
9.
8.
3.
2.
1.
4.
10.
11.
12.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| KM48V2100B | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48C2100C | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode(2M x 8位CMOS 動(dòng)態(tài)RAM(帶快速頁模式)) |
| KM48V2000C | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode(2M x 8位CMOS 動(dòng)態(tài)RAM(帶快速頁模式)) |
| KM48C2000C | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode(2M x 8位CMOS 動(dòng)態(tài)RAM(帶快速頁模式)) |
| KM48V2100C | 2M x 8Bit CMOS Dynamic RAM with Fast Page Mode(2M x 8位CMOS 動(dòng)態(tài)RAM(帶快速頁模式)) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| KM48V2100B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:2M x 8Bit CMOS Dynamic RAM with Fast Page Mode |
| KM48V2104CS-L6 | 制造商:Samsung Semiconductor 功能描述: |
| KM48V8004B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8bit CMOS Dynamic RAM with Extended Data Out |
| KM48V8004C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8bit CMOS Dynamic RAM with Extended Data Out |
| KM48V8104B | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 8bit CMOS Dynamic RAM with Extended Data Out |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。