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參數(shù)資料
| 型號： | KM611001 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 1M x 1Bit High-Speed CMOS SRAM |
| 中文描述： | 100萬x 1位高速CMOS SRAM的 |
| 文件頁數(shù)： | 7/8頁 |
| 文件大?。?/td> | 95K |
| 代理商： | KM611001 |
KM611001/L
CMOS SRAM
Rev 2.0
July-1996
7
NOTES (WRITE CYCLE)
All write cycle timing is referenced from the last valid address to the first transition address.
A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition among
/CS going low and /WE going low; A write ends at the earliest transition among /CS going high and /WE going
high. tWP is measured from the beginning of write to the end of write.
tCW is measured from the later of /CS going low to end of write.
tAS is measured from the address valid to the beginning of write.
tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CS, or /WE
going high.
If /CS goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance
state.
Dout is the read data of the new address.
7.
1.
2.
3.
4.
5.
6.
FUNCTIONAL DESCRIPTION
/CS
/WE
Mode
I/O Pin
Supply Current
H
L
L
X*
H
L
Not Select
Read
Write
High-Z
DOUT
DIN
ISB, ISB1
ICC
ICC
*Note : X means Don't Care.
tSDR
Data Retention Mode
tRDR
/CS Vcc-0.2V
Vcc
4.5V
2.2V
VDR
/CS
GND
DATA RETENTION WAVE FORM
(/CS Controlled)
DATA RETENTION CHARACTERISTICS*
(TA= 0 to 70 °C)
* L-version only
Parameter
Symbol
Test Condition
Min.
Max.
Unit
Vcc for Data Retention
Data Retention Current
Data Retention Set-Up Time
Recovery Time
VDR
IDR
tSDR
tRDR
/CS
Vcc=3.0V, /CS Vcc-0.2V
VIN -0.2V or VIN
See Data Retention
Wave form(below)
5.5
0.1
-
-
V
mA
ns
ms
2.0
-
0
5
≥
Vcc-0.2V
Typ.
-
-
-
-
Vcc
≤
0.2V
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