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| 型號： | KM616FR1010Z |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 64K x 16 Bit Super Low Power and Low Voltage Full CMOS Static RAM(64K x 16位超低功耗低電壓CMOS 靜態(tài)RAM) |
| 中文描述： | 64K的× 16位超低功耗和低電壓的CMOS全靜態(tài)RAM（64K的× 16位超低功耗低電壓的CMOS靜態(tài)RAM）的 |
| 文件頁數(shù)： | 5/9頁 |
| 文件大?。?/td> | 155K |
| 代理商： | KM616FR1010Z |
Revision 0.1
December 1997
CMOS SRAM
KM616FS1010Z, KM616FR1010Z Family
Preliminary
5
AC CHARACTERISTICS
(T
A
=-40 to 85
°
C, KM616FS1010ZI Family:Vcc=2.3 ~3.3V, KM616FS1010ZI Family:Vcc=1.8~2.7V
Parameter List
Symbol
Speed Bins
Units
100ns
150ns
300ns
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
100
-
150
-
300
-
ns
Address access time
t
AA
-
100
-
150
-
300
ns
Chip select to output
t
CO
-
100
-
150
-
300
ns
Output enable to valid output
t
OE
-
50
-
75
-
150
ns
UB, LB Access Time
t
BA
-
100
-
150
-
300
ns
Chip select to low-Z output
t
LZ,
t
BLZ
10
-
20
-
50
-
ns
OE & LB, UB to low-Z output
t
OLZ
5
-
20
-
30
-
ns
Chip disable to high-Z output
t
HZ
0
30
0
40
0
60
ns
OE & LB, UB disable to high-Z
t
OHZ,
t
BHZ
0
30
0
40
0
60
ns
Output hold from address change
t
OH
15
-
15
-
30
-
ns
Write
Write cycle time
t
WC
100
-
150
-
300
-
ns
Chip select to end of write
t
CW
80
-
120
-
300
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
80
-
120
-
300
-
ns
Write pulse width
t
WP
70
-
100
-
200
-
ns
UB, LB Valid to End of Write
t
BW
80
-
120
-
300
-
ns
Write recovery
t
WR
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
30
0
40
0
60
ns
Data to write time overlap
t
DW
40
-
60
-
120
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
20
-
ns
C
L
1)
1. Including scope and jig capacitance
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V/2.3V/1.8V
R
2
3)
R
1
2)
V
TM
3)
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Input/Output Reference)
Input pulse level : 0.4 to 2.2V at Vcc=3.0/2.5V
0.4 to 1.8V at Vcc=2.0V
Input rising and faling time : 5ns
Input and output reference voltage :1.5V at Vcc=3.0V,
1.1V at Vcc=2.5v,
0.9V at Vcc=2.0V
Output load(see right) : C
L
=30pF
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
1)
Min
Typ
-
Max
Unit
Vcc for data retention
V
DR
CS
≥
Vcc-0.2V
Vcc=3.0V, CS
≥
Vcc-0.2V
1.5
3.6
V
Data retention current
I
DR
-
-
5
μ
A
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ns
Recovery time
t
RDR
t
RC
-
-
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