參數(shù)資料
型號： KM616FS1010
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 64K x 16 Bit Super Low Power and Low Voltage Full CMOS Static RAM(64K x 16位超低功耗低電壓CMOS 靜態(tài)RAM)
中文描述： 64K的× 16位超低功耗和低電壓的CMOS全靜態(tài)RAM（64K的× 16位超低功耗低電壓的CMOS靜態(tài)RAM）的
文件頁數(shù)： 5/9頁
文件大小： 116K
代理商： KM616FS1010
Revision 1.0
February 1998
CMOS SRAM
KM616FS1010, KM616FR1010 Family
5
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.4 to 2.2V for Vcc=3.0V, 2.5V
0.4 to 1.8V for Vcc=2.0V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V for Vcc=3.0V
1.1V for Vcc=2.5V
0.9V for Vcc=2.0V
Output load (See right) :C
L
=100pF+1TTL
C
L
=30pF+1TTL
C
L
1)
1. Including scope and jig capacitance
2. R
1
=3070
,
R
2
=3150
3. V
TM
=2.8V for V
CC
=3.0V
=2.3V for V
CC
=2.5V
=1.8V for V
CC
=2.0V
R
2
2)
R
1
2)
V
TM
3)
AC CHARACTERISTICS
(Commercial product :T
A
=0 to 70
°
C, Industrial product : T
A
=-40 to 85
°
C
KM616FS1010 Family : Vcc=2.3~3.3V, KM616FR1010 Family : Vcc=1.8~2.7V)
Parameter List
Symbol
Speed Bins
Units
70ns
85ns
120ns
150ns
300ns
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Read
Read cycle time
t
RC
70
-
85
-
120
-
150
-
300
-
ns
Address access time
t
AA
-
70
-
85
-
120
-
150
-
300
ns
Chip select to output
t
CO
-
70
-
85
-
120
-
150
-
300
ns
Output enable to valid output
t
OE
-
35
-
45
-
60
-
75
-
150
ns
UB, LB Access Time
t
BA
-
70
-
85
-
120
-
150
-
300
ns
Chip select to low-Z output
t
LZ
, t
BLZ
10
-
10
-
20
-
20
-
50
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
20
-
20
-
30
-
ns
Chip disable to high-Z output
t
HZ
0
25
0
25
0
35
0
40
0
60
ns
Output disable to high-Z output
t
OHZ
, t
BHZ
0
25
0
25
0
35
0
40
0
60
ns
Output hold from address change
t
OH
10
-
15
-
15
-
15
-
30
-
ns
Write
Write cycle time
t
WC
70
-
85
-
120
-
150
-
300
-
ns
Chip select to end of write
t
CW
65
-
70
-
100
-
120
-
300
-
ns
Address set-up time
t
AS
0
-
0
-
0
-
0
-
0
-
ns
Address valid to end of write
t
AW
65
-
70
-
100
-
120
-
300
-
ns
Write pulse width
t
WP
55
-
60
-
80
-
100
-
200
-
ns
UB, LB Valid to End of Write
t
BW
65
-
70
-
100
-
120
-
300
-
ns
Write recovery time
t
WR
0
-
0
-
0
-
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
25
0
25
0
35
0
40
0
60
ns
Data to write time overlap
t
DW
30
-
35
-
50
-
60
-
120
-
ns
Data hold from write time
t
DH
0
-
0
-
0
-
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
5
-
5
-
20
-
ns
DATA RETENTION CHARACTERISTICS
1. CS
≥
Vcc-0.2V(CS controlled) or LB=UB
≥
Vcc-0.2V, CS
≤
0.2V(LB, UB controlled)
2. Super low power product=1
μ
A
with special handling.
Item
Symbol
V
DR
Test Condition
Min
1.5
Typ
-
Max
3.6
Unit
V
μ
A
Vcc for data retention
CS
≥
Vcc-0.2V
1)
Vcc=3.0V
Data retention current
I
DR
-
-
5.0
2)
-
Data retention set-up time
t
SDR
See data retention waveform
0
-
ns
Recovery time
t
RDR
t
RC
-
-
相關(guān)PDF資料
PDF描述
KM616FR4010 256K x 16 Bit Low Power and Low Voltage Full CMOS Static RAM(256K x 16位低功耗低電壓CMOS 靜態(tài)RAM)
KM616FS1000Z 64K x 16 Bit Super Low Power and Low Voltage Full CMOS Static RAM(64K x 16位超低功耗低電壓CMOS 靜態(tài)RAM)
KM616FR1000Z 64K x 16 Bit Super Low Power and Low Voltage Full CMOS Static RAM(64K x 16位超低功耗低電壓CMOS 靜態(tài)RAM)
KM616FS1010Z 64K x 16 Bit Super Low Power and Low Voltage Full CMOS Static RAM(64K x 16位超低功耗低電壓CMOS 靜態(tài)RAM)
KM616FR1010Z 64K x 16 Bit Super Low Power and Low Voltage Full CMOS Static RAM(64K x 16位超低功耗低電壓CMOS 靜態(tài)RAM)
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