參數(shù)資料
型號: KM62256DLGI-7
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 32Kx8 bit Low Power CMOS Static RAM
中文描述: 32Kx8位低功耗CMOS靜態(tài)RAM
文件頁數(shù): 5/9頁
文件大?。?/td> 170K
代理商: KM62256DLGI-7
KM62256D Family
CMOS SRAM
Revision 1.0
November 1997
C
L
1)
1. Including scope and jig capacitance
AC OPERATING CONDITIONS
TEST CONDITIONS
(Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :C
L
=100pF+1TTL
C
L
=50pF+1TTL
AC CHARACTERISTICS
(Vcc=4.5~5.5V, KM62256D Family:T
A
=0 to 70
°
C, KM62256DI Family:T
A
=-40 to 85
°
C)
1. The parameter is tested with 50pF test load.
Parameter List
Symbol
Speed Bins
Units
55
1)
ns
70ns
Min
Max
Min
Max
Read
Read cycle time
t
RC
55
-
70
-
ns
Address access time
t
AA
-
55
-
70
ns
Chip select to output
t
CO
-
55
-
70
ns
Output enable to valid output
t
OE
-
25
-
35
ns
Chip select to low-Z output
t
LZ
10
-
10
-
ns
Output enable to low-Z output
t
OLZ
5
-
5
-
ns
Chip disable to high-Z output
t
HZ
0
20
0
30
ns
Output disable to high-Z output
t
OHZ
0
20
0
30
ns
Output hold from address change
t
OH
10
-
10
-
ns
Write
Write cycle time
t
WC
55
-
70
-
ns
Chip select to end of write
t
CW
45
-
60
-
ns
Address set-up time
t
AS
0
-
0
-
ns
Address valid to end of write
t
AW
45
-
60
-
ns
Write pulse width
t
WP
40
-
50
-
ns
Write recovery time
t
WR
0
-
0
-
ns
Write to output high-Z
t
WHZ
0
20
0
25
ns
Data to write time overlap
t
DW
25
-
30
-
ns
Data hold from write time
t
DH
0
-
0
-
ns
End write to output low-Z
t
OW
5
-
5
-
ns
DATA RETENTION CHARACTERISTICS
Item
Symbol
Test Condition
Min
Typ
Max
Unit
Vcc for data retention
V
DR
CS
Vcc-0.2V
2.0
-
5.5
V
Data retention current
I
DR
Vcc=3.0V, CS
Vcc-0.2V
L-Ver
-
1
15
μ
A
LL-Ver
-
0.2
3
Data retention set-up time
t
SDR
See data retention waveform
0
-
-
ms
Recovery time
t
RDR
5
-
-
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