參數(shù)資料
型號(hào): KM718FV4021H-5
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 128Kx36 & 256Kx18 Synchronous Pipelined SRAM
中文描述: 128K × 36至
文件頁(yè)數(shù): 6/20頁(yè)
文件大?。?/td> 536K
代理商: KM718FV4021H-5
512Kx36 & 1Mx18 Synchronous SRAM
- 6 -
Rev 1.0
December 1999
KM718V089
KM736V989
119BGA PACKAGE PIN CONFIGURATIONS
(TOP VIEW)
KM718V089(1Mx18)
Note :
* A
0
and A
1
are the two least significant bits(LSB) of the address field and set the internal burst counter if burst is desired.
1
2
3
4
5
6
7
A
V
DDQ
A
A
ADSP
A
A
V
DDQ
B
NC
A
A
ADSC
A
A
NC
C
NC
A
A
V
DD
A
A
NC
D
DQb
NC
V
SS
NC
V
SS
DQPa
NC
E
NC
DQb
V
SS
CS
1
V
SS
NC
DQa
F
V
DDQ
NC
V
SS
OE
V
SS
DQa
V
DDQ
G
NC
DQb
WEb
ADV
V
SS
NC
DQa
H
DQb
NC
V
SS
GW
V
SS
DQa
NC
J
V
DDQ
V
DD
NC
V
DD
NC
V
DD
V
DDQ
K
NC
DQb
V
SS
CLK
V
SS
NC
DQa
L
DQb
NC
V
SS
NC
WEa
DQa
NC
M
V
DDQ
DQb
V
SS
BW
V
SS
NC
V
DDQ
N
DQb
NC
V
SS
A
1
*
V
SS
DQa
NC
P
NC
DQPb
V
SS
A
0
*
V
SS
NC
DQa
R
NC
A
LBO
V
DD
NC
A
NC
T
NC
A
A
NC
A
A
ZZ
U
V
DDQ
NC
NC
NC
NC
NC
V
DDQ
PIN NAME
SYMBOL
PIN NAME
SYMBOL
PIN NAME
A
A
0
,A
1
ADV
ADSP
ADSC
CLK
CS
1
WEx
(x=a,b)
OE
GW
BW
ZZ
LBO
Address Inputs
Burst Count Address
Burst Address Advance
Address Status Processor
Address Status Controller
Clock
Chip Select
Byte Write Inputs
Output Enable
Global Write Enable
Byte Write Enable
Power Down Input
Burst Mode Control
V
DD
V
SS
N.C.
DQa
DQb
DQPa~Pb
V
DDQ
Power Supply(+3.3V)
Ground
No Connect
Data Inputs/Outputs
Data Inputs/Outputs
Data Inputs/Outpus
Output Power Supply
(2.5V or 3.3V)
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