參數(shù)資料
型號(hào): KMC7448VS1700LC
廠商: Freescale Semiconductor
文件頁數(shù): 33/60頁
文件大?。?/td> 0K
描述: IC MPU 128BIT 1700MHZ 360-FCCLGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC74xx
處理器類型: 32-位 MPC74xx PowerPC
速度: 1.7GHz
電壓: 1.3V
安裝類型: 表面貼裝
封裝/外殼: 360-CLGA,F(xiàn)CCLGA
供應(yīng)商設(shè)備封裝: 360-FCCLGA(25x25)
包裝: 托盤
MPC7448 RISC Microprocessor Hardware Specifications, Rev. 4
Freescale Semiconductor
39
System Design Information
Figure 17. MPC7448 Power Down Sequencing Requirements
There is no requirement regarding AVDD during power down, but it is recommended that AVDD track VDD
within the RC time constant of the PLL filter circuit described in Section 9.2.2, “PLL Power Supply
Filtering” (nominally 100 s).
9.2.2
PLL Power Supply Filtering
The AVDD power signal is provided on the MPC7448 to provide power to the clock generation PLL. To
ensure stability of the internal clock, the power supplied to the AVDD input signal should be filtered of any
noise in the 500-KHz to 10-MHz resonant frequency range of the PLL. The circuit shown in Figure 18
using surface mount capacitors with minimum effective series inductance (ESL) is strongly recommended.
In addition to filtering noise from the AVDD input, it also provides the required delay between VDD and
The circuit should be placed as close as possible to the AVDD pin to minimize noise coupled from nearby
circuits. It is often possible to route directly from the capacitors to the AVDD pin, which is on the periphery
of the device footprint.
Figure 18. PLL Power Supply Filter Circuit
VDD
OVDD
no restrictions between VDD and OVDD
SYSCLK
0.9 V
AVDD
no restrictions between VDD and AVDD
note also restrictions between SYSCLK and OVDD
0.9 V
limit imposed by VDD if VDD ramps down first
limit imposed by OVDD if OVDD ramps down first
VDD
AVDD
10
Ω
2.2 F
GND
Low ESL Surface Mount Capacitors
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