參數(shù)資料
型號(hào): KMC7457RX1267LC
廠(chǎng)商: Freescale Semiconductor
文件頁(yè)數(shù): 25/71頁(yè)
文件大?。?/td> 0K
描述: IC MPU RISC 32BIT 1267MHZ 483BGA
標(biāo)準(zhǔn)包裝: 1
系列: MPC74xx
處理器類(lèi)型: 32-位 MPC74xx PowerPC
速度: 1.267GHz
電壓: 1.3V
安裝類(lèi)型: 表面貼裝
封裝/外殼: 483-BCBGA,F(xiàn)CCBGA
供應(yīng)商設(shè)備封裝: 483-FCCBGA(29x29)
包裝: 托盤(pán)
Electrical and Thermal Characteristics
MPC7457 RISC Microprocessor Hardware Specifications, Rev. 8
Freescale Semiconductor
31
Table 14. L3 Bus Interface AC Timing Specifications for PB2 and Late Write SRAMs
At recommended operating conditions. See Table 4.
Parameter
Symbol
All Revisions and L3 I/O
Voltage Modes
Unit
Notes
Min
Max
L3_CLK rise and fall time
tL3CR, tL3CF
—0.75
ns
1, 2
Setup times: Data and parity
tL3DVEH
0.1
ns
2, 3
Input hold times: Data and parity
tL3DXEH
0.7
ns
2, 3
Valid times: Data and parity
tL3CHDV
2.5
ns
2, 4, 5
Valid times: All other outputs
tL3CHOV
—1.8
ns
5
Output hold times: Data and parity
tL3CHDX
1.4
ns
2, 4, 5
Output hold times: All other outputs
tL3CHOX
1.0
ns
2, 5
L3_CLK to high impedance: Data and parity
tL3CHDZ
—3.0
ns
2
L3_CLK to high impedance: All other outputs
tL3CHOZ
—3.0
ns
2
Notes:
1. Rise and fall times for the L3_CLK output are measured from 20% to 80% of GVDD.
2. Timing behavior and characterization are currently being evaluated.
3. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L3_ECHO_CLK
n (see Figure 10). Input timings are measured at the pins.
4. All output specifications are measured from the midpoint voltage of the rising edge of L3_CLK
n to the midpoint of the signal
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see
5. Assumes default value of L3OHCR. See Section 5.2.4.1, “Effects of L3OHCR Settings on L3 Bus AC Specifications,” for more
information.
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