參數(shù)資料
型號： KMC755CVT400LE
廠商： Freescale Semiconductor
文件頁數(shù)： 13/56頁
文件大小： 0K
描述： IC MPU 32BIT 400MHZ 360-FCPBGA
標準包裝： 1
系列： MPC7xx
處理器類型： 32-位 MPC7xx PowerPC
速度： 400MHz
電壓： 2V
安裝類型： 表面貼裝
封裝/外殼： 360-BBGA，F(xiàn)CCBGA
供應商設備封裝： 360-FCCBGA（25x25）
包裝： 托盤
MPC755 RISC Microprocessor Hardware Specifications, Rev. 8
20
Freescale Semiconductor
Electrical and Thermal Characteristics
Figure 8 shows the L2 bus input timing diagrams for the MPC755.
Figure 8. L2 Bus Input Timing Diagrams
L2SYNC_IN to high impedance:
All outputs when L2CR[14–15] = 00
All outputs when L2CR[14–15] = 01
All outputs when L2CR[14–15] = 10
All outputs when L2CR[14–15] = 11
tL2CHOZ
—
2.4
2.6
2.8
3.0
ns
3, 5
Notes:
1. Rise and fall times for the L2SYNC_IN input are measured from 20% to 80% of L2OVDD.
2. All input specifications are measured from the midpoint of the signal in question to the midpoint voltage of the rising edge of
the input L2SYNC_IN (see Figure 8). Input timings are measured at the pins.
3. All output specifications are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint of the
signal in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-
Ω load (see
4. The outputs are valid for both single-ended and differential L2CLK modes. For pipelined registered synchronous BurstRAMs,
L2CR[14–15] = 01 or 10 is recommended. For pipelined late write synchronous BurstRAMs, L2CR[14–15] = 11 is
recommended.
5. Guaranteed by design and characterization.
6. Revisions prior to Rev. 2.8 (Rev. E) were limited in performance and did not conform to this specification. For more
Table 12. L2 Bus Interface AC Timing Specifications (continued)
At recommended operating conditions (see Table 3)
Parameter
Symbol
All Speed Grades
Unit
Notes
Min
Max
L2SYNC_IN
L2 Data and Data
VM
VM = Midpoint Voltage (L2OVDD/2)
tDVL2CH
tDXL2CH
tL2CR
tL2CF
Parity Inputs
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