參數(shù)資料
型號(hào)： KMC8112TVT2400V
廠商： Freescale Semiconductor
文件頁數(shù)： 16/44頁
文件大小： 0K
描述： IC DSP 300MHZ 431FCPBGA
標(biāo)準(zhǔn)包裝： 2
系列： StarCore
類型： SC140 內(nèi)核
接口： 以太網(wǎng)，I²C，TDM，UART
時(shí)鐘速率： 300MHz
非易失內(nèi)存： 外部
芯片上RAM： 448kB
電壓 - 輸入/輸出： 3.30V
電壓 - 核心： 1.10V
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 431-BFBGA，F(xiàn)CBGA
供應(yīng)商設(shè)備封裝： 431-FCPBGA（20x20）
包裝： 托盤
Electrical Characteristics
MSC8112 Dual Core Digital Signal Processor Data Sheet, Rev. 1
Freescale Semiconductor
23
Table 15. AC Timing for SIU Outputs
No.
Characteristic
Bus Speed in MHz3
Ref = CLKIN at 1.1 V
and 100 MHz
Units
302
Minimum delay from the 50% level of the REFCLK for all signals
0.9
ns
31
PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge
6.0
ns
32a
Address bus max delay from the 50% level of the REFCLK rising edge
Multi-master mode (SIUBCR[EBM] = 1)
Single-master mode (SIUBCR[EBM] = 0)
6.4
5.3
ns
32b
Address attributes: TT[0–1]/TBST/TSZ/GBL max delay from the 50% level
of the REFCLK rising edge
6.4
ns
32c
Address attributes: TT[2–4]/TC max delay from the 50% level of the
REFCLK rising edge
6.9
ns
32d
BADDR max delay from the 50% level of the REFCLK rising edge
5.2
ns
33a
Data bus max delay from the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
4.8
7.1
ns
33b
DP max delay from the 50% level of the REFCLK rising edge
Data-pipeline mode
Non-pipeline mode
6.0
7.5
ns
34
Memory controller signals/ALE/CS[0–4] max delay from the 50% level of
the REFCLK rising edge
5.1
ns
35a
DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising
edge
6.0
ns
35b
AACK/ABB/TS/CS[5–7] max delay from the 50% level of the REFCLK
rising edge
5.5
ns
Notes:
1.
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level and assume a 20 pF load except
where otherwise specified.
2.
Except for specification 30, which is specified for a 10 pF load, all timings in this table are specified for a 20 pF load.
Decreasing the load results in a timing decrease at the rate of 0.3 ns per 5 pF decrease in load. Increasing the load results in
a timing increase at the rate of 0.15 ns per 5 pF increase in load.
3.
The maximum bus frequency depends on the mode:
In 60x-compatible mode connected to another MSC8112 device, the frequency is determined by adding the input and output
longest timing values, which results in the total delay for 20 pF output capacitance. You must also account for other
influences that can affect timing, such as on-board clock skews, on-board noise delays, and so on.
In single-master mode, the frequency depends on the timing of the devices connected to the MSC8112.
To achieve maximum performance on the bus in single-master mode, disable the DBB signal by writing a 1 to the
SIUMCR[BDD] bit. See the SIU chapter in the MSC8112 Reference Manual for details.
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