參數(shù)資料
型號: KMC9328MX1DVM20
廠商: Freescale Semiconductor
文件頁數(shù): 30/100頁
文件大?。?/td> 0K
描述: IC MCU I.MX 200MHZ 256-MAPBGA
標(biāo)準(zhǔn)包裝: 1
系列: i.MX1
核心處理器: ARM9
芯體尺寸: 32-位
速度: 200MHz
連通性: EBI/EMI,I²C,MMC,智能卡,SPI,SSI,UART/USART,USB
外圍設(shè)備: DMA,I²S,LCD,POR,PWM,WDT
輸入/輸出數(shù): 110
程序存儲器類型: ROMless
電壓 - 電源 (Vcc/Vdd): 1.7 V ~ 3.3 V
振蕩器型: 外部
工作溫度: -30°C ~ 70°C
封裝/外殼: 256-LBGA
包裝: 托盤
Functional Description and Application Information
MC9328MX1 Technical Data, Rev. 7
Freescale Semiconductor
35
4.4.3
EIM External Bus Timing
The External Interface Module (EIM) is the interface to devices external to the i.MX1, including
generation of chip-selects for external peripherals and memory. The timing diagram for the EIM is shown
in Figure 5, and Table 12 defines the parameters of signals.
Table 16. WAIT Write Cycle DMA Enabled: WSC = 111111, DTACK_SEL=1, HCLK=96MHz
Number
Characteristic
3.0 ± 0.3 V
Unit
Minimum
Maximum
1
CS5 assertion time
See note 2
ns
2EB assertion time
See note 2
ns
3CS5 pulse width
3T
ns
4RW negated before CS5 is negated
2.5T-0.29
2.5T+0.68
ns
5
Address inactived after CS negated
0.93
ns
6
Wait asserted after CS5 asserted
1020T
ns
7
Wait asserted to RW negated
T+2.15
2T+7.34
ns
8
Data hold timing after RW negated
24.87
ns
9
Data ready after CS5 is asserted
T
ns
10
CS deactive to next CS active
T
ns
11
EB negate after CS negate
1.5T+0.74
1.5T+2.35
12
Wait becomes low after CS5 asserted
0
1019T
ns
13
Wait pulse width
1T
1020T
ns
Note:
1. T is the system clock period. (For 96 MHz system clock, T=10.42 ns)
2. CS5 assertion can be controlled by CSA bits. EB assertion also can be programmable by WEA bits in CS5L register.
3. Address becomes valid and RW asserts at the start of write access cycle.
4.The external wait input requirement is eliminated when CS5 is programmed to use internal wait state.
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