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參數(shù)資料
| 型號(hào)： | KMM364E410CK |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 4Mx64 DRAM DIMM(4Mx64 動(dòng)態(tài) RAM模塊) |
| 中文描述： | 4Mx64的DRAM內(nèi)存（4Mx64動(dòng)態(tài)內(nèi)存模塊） |
| 文件頁(yè)數(shù)： | 5/20頁(yè) |
| 文件大?。?/td> | 391K |
| 代理商： | KMM364E410CK |
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DRAM MODULE
KMM364E410CK/CS
KMM364E400CK/CS
Test condition : V
ih
/V
il
=2.4/0.8V, V
oh
/V
ol
=2.0/0.8V, Output loading CL=100pF
Parameter
Symbol
-5
-6
Unit
Note
Min
71
48
53
5
8
3
20
Max
Min
83
55
60
5
8
3
20
Max
RAS to W dealy time
Column address to W delay time
CAS precharge time to W delay time
CAS set-up time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
CAS precharge time (C-B-R counter test cycle)
Access time from CAS precharge
Hyper page cycle time
Hyper page read-modify-write cycle time
CAS precharge time(Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
Output data hold time
Output buffer turn off delay time from RAS
Output buffer turn off delay time from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width(Hyper page cycle)
t
RWD
t
AWD
t
CPWD
t
CSR
t
CHR
t
RPC
t
CPT
t
CPA
t
HPC
t
HPRWC
t
CP
t
RASP
t
RHCP
t
OEA
t
OED
t
OEZ
t
OEH
t
WRP
t
WRH
t
DOH
t
REZ
t
WEZ
t
WED
t
OCH
t
CHO
t
OEP
t
WPE
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
7,14
7
14
14
14
33
40
3,14
13
13
25
68
8
50
35
30
77
10
60
40
200K
200K
14
14
14
18
20
18
5
13
15
8
10
3
3
20
5
5
5
5
20
5
15
15
8
10
3
3
20
5
5
5
5
18
20
6,11,14
14
14
14
13
18
15
20
6,11,12
6,11,14
14
PDE to Valid PD bit
PDE to PD bit Inactive
t
PD
t
PDOFF
10
7
10
7
ns
ns
2
2
Present Detect Read Cycle
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C, V
CC
=5.0V
±
10%. See notes 1,2.)
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