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參數(shù)資料
| 型號(hào)： | KMM372C883CS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 8M x 72 DRAM DIMM with ECC using 8Mx8, 4K 8K Refresh, 5V |
| 中文描述： | 8米× 72的DRAM內(nèi)存的ECC的使用8Mx8，4K的8K的刷新，5V的 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大小： | 425K |
| 代理商： | KMM372C883CS |
DRAM MODULE
KMM372C80(8)3CK/CS
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are V
ih
/V
il
. V
IH
(min) and V
IL
(max) are ref-
erence levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 2 TTL loads and 100pF.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPWD
are not restrictive operat-
ing parameter. They are included in the data sheet as electri-
cal characteristics only. If
t
WCS
≥
t
WCS
(min) the cycle is an
early write cycle and the data out pin will remain high imped-
ance for the duration of the cycle. If
t
RWD
≥
t
RWD
(min),
t
CWD
≥
t
CWD
(min),
t
AWD
≥
t
AWD
(min) and
t
CPWD
≥
t
CPWD
(min).
The cycle is a read-modify-write cycle and the data out will
contain data read from the selected cell. If neither of the
above sets of conditions is satisfied, the condition of data
out(at access time) is indeterminate.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
AC CHARACTERISTICS
(0
°
C
≤
T
A
≤
70
°
C, V
CC
=5.0V
±
10%. See notes 1,2.)
Parameter
Symbol
-5
-6
Unit
Note
Min
10
8
3
Max
Min
10
8
3
Max
CAS setup time(CAS-before-RAS refresh)
CAS hold time(CAS-before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Fast page mode cycle time
Fast page mode read-modify-write cycle time
CAS precharge time(Fast page cycle)
RAS pulse width(Fast page cycle)
RAS hold time from CAS precharge
W to RAS precharge time(C-B-R refresh)
W to RAS hold time(C-B-R refresh)
OE access time
OE to data delay
Output buffer turn off delay time from OE
OE command hold time
t
CSR
t
CHR
t
RPC
t
CPA
t
PC
t
PRWC
t
CP
t
RASP
t
RHCP
t
WRP
t
WRH
t
OEA
t
OED
t
OEZ
t
OEH
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
11
11
11
3,11
35
40
35
76
10
50
35
15
8
40
85
10
60
40
15
8
200K
200K
11
11
11
11
11
11
18
20
18
5
13
20
5
15
18
20
PDE to Valid PD bit
PDE to PD bit Inactive
t
PD
t
PDOFF
10
7
10
7
ns
ns
2
2
Present Detect Read Cycle
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