參數(shù)資料
型號： KMM372F410CK
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： 4M x 72 DRAM DIMM with ECC using 4Mx4, 4K 2K Refresh, 3.3V
中文描述： 4米× 72的DRAM內(nèi)存的ECC的使用4Mx4，4K的2K刷新，3.3
文件頁數(shù)： 6/20頁
文件大?。?/td> 456K
代理商： KMM372F410CK
DRAM MODULE
KMM372F410CK/CS
KMM372F400CK/CS
NOTES
An initial pause of 200us is required after power-up followed
by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. V
IH
(min) and V
IL
(max) are
reference levels for measuring timing of input signals. Transi-
tion times are measured between V
IH
(min) and V
IL
(max) and
are assumed to be 5ns for all inputs.
Measured with a load equivalent to 1TTL loads and 100pF.
Voh=2.0V and Vol=0.8V.
Operation within the
t
RCD
(max) limit insures that
t
RAC
(max)
can be met.
t
RCD
(max) is specified as a reference point only.
If
t
RCD
is greater than the specified
t
RCD
(max) limit, then
access time is controlled exclusively by
t
CAC
.
Assumes that
t
RCD
≥
t
RCD
(max).
This parameter defines the time at which the output achieves
the open circuit condition and is not referenced to V
OH
or
V
OL
.
t
WCS
,
t
RWD
,
t
CWD
and
t
AWD
are non restrictive operating
parameter. They are included in the data sheet as electrical
characteristics only. If
t
WCS
≥
t
WCS
(min) the cycle is an early
write cycle and the data out pin will remain high impedance
for the duration of the cycle.
If
t
CWD
≥
t
CWD
(min),
t
RWD
≥
t
RWD
(min) and
t
AWD
≥
t
AWD
(min),
then the cycle is a read-write cycle and the data output will
contain data read from the selected address. If neither of the
above conditions are satisfied, the condition of the data out
is indeterminated.
Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
These parameters are referenced to the CAS leading edge in
early write cycles and to the W leading edge in read-write
cycles.
Operation within the
t
RAD
(max) limit insures that
t
RAC
(max)
can be met.
t
RAD
(max) is specified as reference point only. If
t
RAD
is greater than the specified
t
RAD
(max) limit, then
access time is controlled by
t
AA
.
t
CEZ
(max),
t
REZ
(max),
t
WEZ
(max) and
t
OEZ
(max) define the
time at which the output achieves the open circuit condition
and are not referenced to output voltage level.
If RAS goes to high before CAS high going, the open circuit
condition of the output is achieved by CAS high going. If CAS
goes to high before RAS high going , the open circuit condi-
tion of the output is achieved by RAS high going.
t
ASC
≥
t
CP
min
The timing skew from the DRAM to the DIMM resulted from
the addition of buffers.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
12.
13.
11.
14.
相關(guān)PDF資料
PDF描述
KMM372F803BK 8M x 72 DRAM DIMM(8Mx72 動態(tài) RAM模塊)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
KMM372F410CS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:4M x 72 DRAM DIMM with ECC using 4Mx4, 4K 2K Refresh, 3.3V
KMM372F803BK 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 72 DRAM DIMM with ECC using 8Mx8, 4K 8K Refresh, 3.3V
KMM372F803BS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 72 DRAM DIMM with ECC using 8Mx8, 4K 8K Refresh, 3.3V
KMM372F804BS 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 72 DRAM DIMM with ECC using 4Mx16, 4Mx4 4K Refresh, 3.3V
KMM372F883BK 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:8M x 72 DRAM DIMM with ECC using 8Mx8, 4K 8K Refresh, 3.3V
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