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參數(shù)資料
| 型號(hào)： | KMM965G512 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512Kx64 SGRAM SODIMM(512Kx64 圖形RAM模塊) |
| 中文描述： | 512Kx64 SGRAM個(gè)SODIMM（512Kx64圖形內(nèi)存模塊） |
| 文件頁數(shù)： | 3/15頁 |
| 文件大?。?/td> | 148K |
| 代理商： | KMM965G512 |
SGRAM MODULE
KMM965G512BQ(P)N / KMM966G512BQ(P)N
ELECTRONICS
- 4 -
Rev. 2.5 (July. 1998)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System Clock
Active on the positive going edge to sample all inputs.
CS
Chip Select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock Enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one clock + t
SS
prior to new command.
Disable input buffers for power down in standby.
A0 ~ A8
Address
Row / column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA8, column address : CA0 ~ CA7
BA(A9)
Bank Select Address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row Address Strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column Address Strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write Enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
DQM0 ~ 7
Data Input/Output Mask
Makes data output Hi-Z, t
SHZ
after the clock and masks the output.
Blocks data input when DQM active. (Byte masking)
DQ0 ~ 63
Data Input/Output
Data inputs/outputs are multiplexed on the same pins.
DSF
Define Special Function
Enables write per bit, block write and special mode register set.
V
DD
/V
SS
Power Supply/Ground
Power and ground for the input buffers and the core logic.
Three resistor straps are used to indicate the synchronous clock frequency (period) and memory timing.Timing information
for each clock frequency is indicated in the section titled
AC CHARATERISTICS
.
Clock Frequency and Memory Timing
CAS Latency
Cycle Time
DQ30
DQ29
15 ns
0
0
12 ns
0
1
10 ns
1
0
8ns
1
1
CAS Latency
DQ31
3
0
2 and 3
1
RESISTOR STRAPPING OPTIONS
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