參數(shù)資料
型號： KMPC8248ZQTIEA
廠商： Freescale Semiconductor
文件頁數(shù)： 56/61頁
文件大小： 0K
描述： IC MPU PWRQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝： 2
系列： MPC82xx
處理器類型： 32-位 MPC82xx PowerQUICC II
速度： 400MHz
電壓： 1.5V
安裝類型： 表面貼裝
封裝/外殼： 516-BBGA
供應(yīng)商設(shè)備封裝： 516-FPBGA（27x27）
包裝： 托盤
MPC8272 PowerQUICC II Family Hardware Specifications, Rev. 3
6
Freescale Semiconductor
Overview
– One of the FCCs supports ATM (MPC8272 and MPC8271 only)—full-duplex SAR at 155
Mbps, 8-bit UTOPIA interface 31 Mphys, AAL5, AAL1, AAL2, AAL0 protocols, TM 4.0
CBR, VBR, UBR, ABR traffic types, up to 64-K external connections
— Three serial communications controllers (SCCs) identical to those on the MPC860 supporting
the digital portions of the following protocols:
– Ethernet/IEEE 802.3 CDMA/CS
– HDLC/SDLC and HDLC bus
– Universal asynchronous receiver transmitter (UART)
– Synchronous UART
– Binary synchronous (BiSync) communications
– Transparent
– QUICC multichannel controller (QMC) up to 64 channels
Independent transmit and receive routing, frame synchronization.
Serial-multiplexed (full-duplex) input/output 2048, 1544, and 1536 Kbps PCM
highways
Compatible with T1/DS1 24-channel and CEPT E1 32-channel PCM highway, ISDN
basic rate, ISDN primary rate, and user defined.
Subchanneling on each time slot.
Independent transmit and receive routing, frame synchronization and clocking
Concatenation of any not necessarily consecutive time slots to channels independently
for receiver/transmitter
Supports H1,H11, and H12 channels
Allows dynamic allocation of channels
– SCC3 in NMSI mode is not usable when USB is enabled.
— Two serial management controllers (SMCs), identical to those of the MPC860
– Provides management for BRI devices as general-circuit interface (GCI) controllers in
time-division-multiplexed (TDM) channels
– Transparent
– UART (low-speed operation)
— One serial peripheral interface identical to the MPC860 SPI
— One I2C controller (identical to the MPC860 I2C controller)
– Microwire compatible
– Multiple-master, single-master, and slave modes
— Up to two TDM interfaces
– Supports one group
s of two TDM channels
– 1024 bytes of SI RAM
— Eight independent baud rate generators and 14 input clock pins for supplying clocks to FCC,
SCC, SMC, and USB serial channels
— Four independent 16-bit timers that can be interconnected as two 32-bit timers
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