參數(shù)資料
型號: KMPC8313CVRAFFB
廠商: Freescale Semiconductor
文件頁數(shù): 86/99頁
文件大小: 0K
描述: IC MPU POWERQUICC II 516-PBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應商設備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
87
21.3
Heat Sink Attachment
When attaching heat sinks to these devices, an interface material is required. The best method is to use
thermal grease and a spring clip. The spring clip should connect to the printed-circuit board, either to the
board itself, to hooks soldered to the board, or to a plastic stiffener. Avoid attachment forces which would
lift the edge of the package or peel the package from the board. Such peeling forces reduce the solder joint
lifetime of the package. Recommended maximum force on the top of the package is 10 lb (4.5 kg) force.
If an adhesive attachment is planned, the adhesive should be intended for attachment to painted or plastic
surfaces and its performance verified under the application requirements.
21.3.1
Experimental Determination of the Junction Temperature with a
Heat Sink
When heat sink is used, the junction temperature is determined from a thermocouple inserted at the
interface between the case of the package and the interface material. A clearance slot or hole is normally
required in the heat sink. Minimizing the size of the clearance is important to minimize the change in
thermal performance caused by removing part of the thermal interface to the heat sink. Because of the
experimental difficulties with this technique, many engineers measure the heat sink temperature and then
back calculate the case temperature using a separate measurement of the thermal resistance of the
interface. From this case temperature, the junction temperature is determined from the junction to case
thermal resistance.
TJ = TC + (RJC x PD)
where:
TJ = junction temperature (C)
TC = case temperature of the package
RJC = junction-to-case thermal resistance
PD = power dissipation
22 System Design Information
This section provides electrical and thermal design recommendations for successful application of the
MPC8313E SYS_CLK_IN
22.1
System Clocking
The MPC8313E includes three PLLs.
1. The platform PLL (AVDD2) generates the platform clock from the externally supplied
SYS_CLK_IN input in PCI host mode or SYS_CLK_IN/PCI_SYNC_IN in PCI agent mode. The
frequency ratio between the platform and SYS_CLK_IN is selected using the platform PLL ratio
configuration bits as described in Section 20.1, “System PLL Configuration.”
2. The e300 core PLL (AVDD1) generates the core clock as a slave to the platform clock. The
frequency ratio between the e300 core clock and the platform clock is selected using the e300
PLL ratio configuration bits as described in Section 20.2, “Core PLL Configuration.”
3. There is a PLL for the SerDes block.
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