參數(shù)資料
型號(hào): KMPC8313CVRAGDB
廠商: Freescale Semiconductor
文件頁數(shù): 59/99頁
文件大小: 0K
描述: IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
62
Freescale Semiconductor
18.2 SPI AC Timing Specifications
This table and provide the SPI input and output AC timing specifications.
This figure provides the AC test load for the SPI.
Figure 53. SPI AC Test Load
Figure 54 and Figure 55 represent the AC timing from Table 61. Note that although the specifications
generally reference the rising edge of the clock, these AC timing diagrams also apply when the falling edge
is the active edge.
Input high voltage
VIH
—2.1
NVDD +0.3
V
Input low voltage
VIL
—–0.3
0.8
V
Input current
IIN
0 V
V
IN NVDD
±5
A
Table 61. SPI AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
SPI outputs—master mode (internal clock) delay
tNIKHOV
0.5
6
ns
SPI outputs—slave mode (external clock) delay
tNEKHOV
28
ns
SPI inputs—master mode (internal clock) input setup time
tNIIVKH
6—
ns
SPI inputs—master mode (internal clock) input hold time
tNIIXKH
0—
ns
SPI inputs—slave mode (external clock) input setup time
tNEIVKH
4—
ns
SPI inputs—slave mode (external clock) input hold time
tNEIXKH
2—
ns
Note:
1. Output specifications are measured from the 50% level of the rising edge of SYS_CLK_IN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for inputs
and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tNIKHOV symbolizes the NMSI outputs
internal timing (NI) for the time tSPI memory clock reference (K) goes from the high state (H) until outputs (O) are valid (V).
Table 60. SPI DC Electrical Characteristics (continued)
Characteristic
Symbol
Condition
Min
Max
Unit
Output
Z0 = 50
NVDD/2
RL = 50
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