參數(shù)資料
型號: KMPC8313EVRAFFB
廠商: Freescale Semiconductor
文件頁數(shù): 40/99頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 516-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 333MHz
電壓: 0.95 V ~ 1.05 V
安裝類型: 表面貼裝
封裝/外殼: 516-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 516-PBGAPGE(27x27)
包裝: 托盤
MPC8313E PowerQUICC II Pro Processor Hardware Specifications, Rev. 4
Freescale Semiconductor
45
10 USB
10.1
USB Dual-Role Controllers
This section provides the AC and DC electrical specifications for the USB interface.
10.1.1
USB DC Electrical Characteristics
This table provides the DC electrical characteristics for the USB interface.
10.1.2
USB AC Electrical Specifications
This table describes the general timing parameters of the USB interface.
The following two figures provide the AC test load and signals for the USB, respectively.
Figure 34. USB AC Test Load
Table 40. USB DC Electrical Characteristics
Parameter
Symbol
Min
Max
Unit
High-level input voltage
VIH
2.0
LVDDB +0.3
V
Low-level input voltage
VIL
–0.3
0.8
V
Input current
IIN
—±5
A
High-level output voltage, IOH = –100 AVOH
LVDDB – 0.2
V
Low-level output voltage, IOL = 100 AVOL
—0.2
V
Table 41. USB General Timing Parameters (ULPI Mode Only)
Parameter
Symbol1
Min
Max
Unit
Note
USB clock cycle time
tUSCK
15
ns
Input setup to USB clock—all inputs
tUSIVKH
4—
ns
input hold to USB clock—all inputs
tUSIXKH
1—
ns
USB clock to output valid—all outputs
tUSKHOV
—7
ns
Output hold from USB clock—all outputs
tUSKHOX
2—
ns
Note:
1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tUSIXKH symbolizes USB timing
(USB) for the input (I) to go invalid (X) with respect to the time the USB clock reference (K) goes high (H). Also, tUSKHOX
symbolizes us timing (USB) for the USB clock reference (K) to go high (H), with respect to the output (O) going invalid (X)
or output hold time.
Output
Z0 = 50
NVDD/2
RL = 50
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