參數(shù)資料
型號(hào): KMPC8314ECVRAGDA
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 8/101頁(yè)
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 620-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1V
安裝類型: 表面貼裝
封裝/外殼: 620-BBGA 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 620-PBGA(29x29)
包裝: 托盤(pán)
MPC8314E PowerQUICC II Pro Processor Hardware Specifications, Rev. 2
14
Freescale Semiconductor
Clock Input Timing
5.1
DC Electrical Characteristics
This table provides the clock input (SYS_CLK_IN/PCI_SYNC_IN) DC timing specifications for the
MPC8314E.
5.2
AC Electrical Characteristics
The primary clock source for the MPC8314E can be one of two inputs, SYS_CLK_IN or PCI_CLK,
depending on whether the device is configured in PCI host or PCI agent mode. This table provides the
clock input (SYS_CLK_IN/PCI_CLK) AC timing specifications for the MPC8314E.
Table 6. SYS_CLK_IN DC Electrical Characteristics
Parameter
Condition
Symbol
Min
Max
Unit
Input high voltage
VIH
2.4
NVDD + 0.3
V
Input low voltage
VIL
-0.3
0.4
V
SYS_CLK_IN input current
0 V
V
IN NVDD
IIN
—±10
A
SYS_XTAL_IN input current
0 V
V
IN NVDD
IIN
—±40
A
PCI_SYNC_IN input current
0 V
V
IN NVDD
IIN
—±10
A
RTC_CLK input current
0 V
V
IN NVDD
IIN
—±10
A
USB_CLK_IN input current
0 V
V
IN NVDD
IIN
—±10
A
USB_XTAL_IN input current
0 V
V
IN NVDD
IIN
—±40
A
Table 7. SYS_CLK_IN AC Timing Specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
SYS_CLK_IN/PCI_CLK frequency
fSYS_CLK_IN
24
66.67
MHz
1, 6, 7
SYS_CLK_IN/PCI_CLK cycle time
tSYS_CLK_IN
15
41.6
ns
6
SYS_CLK_IN rise and fall time
tKH, tKL
0.6
4
ns
2, 6
PCI_CLK rise and fall time
tPCH, tPCL
0.6
0.8
1.2
ns
2
SYS_CLK_IN/PCI_CLK duty cycle
tKHK/tSYS_CLK_IN
40
60
%
3, 6
SYS_CLK_IN/PCI_CLK jitter
±150
ps
4, 5, 6
Note:
1. Caution: The system, core, and security block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYS_CLK_IN/PCI_CLK are specified at 20% to 80% of signal swing.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN/PCI_CLK driver’s closed loop jitter bandwidth should be <500 kHz at –20 dB. The bandwidth must be set
low to allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. The parameter names PCI_CLK and PCI_SYNC_IN are used interchangeably in this document.
7. Spread spectrum is allowed up to 1% down-spread at 33kHz.(max. rate).
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