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| 型號(hào)： | KMPC8323ZQAFDC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 63/82頁 |
| 文件大小： | 0K |
| 描述： | IC MPU PWRQUICC II 516PBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 333MHz |
| 電壓： | 1V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 516-BBGA |
| 供應(yīng)商設(shè)備封裝： | 516-FPBGA（27x27） |
| 包裝： | 托盤 |
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MPC8323E PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 4
66
Freescale Semiconductor
Clocking
The ce_clk frequency is determined by the QUICC Engine PLL multiplication factor (RCWL[CEPMF)
and the QUICC Engine PLL division factor (RCWL[CEPDF]) according to the following equation:
When CLKIN is the primary input clock,
ce_clk = (primary clock input × CEPMF)
÷ (1 + CEPDF)
When PCI_CLK is the primary input clock,
ce_clk = [primary clock input × CEPMF × (1 + ~CFG_CLKIN_DIV)] ÷ (1 + CEPDF)
See the “QUICC Engine PLL Multiplication Factor” section and the “QUICC Engine PLL Division
Factor” section in the MPC8323E PowerQUICC II Pro Communications Processor Reference Manual for
more information.
The DDR SDRAM memory controller operates with a frequency equal to twice the frequency of csb_clk.
Note that ddr_clk is not the external memory bus frequency; ddr_clk passes through the DDR clock divider
(
÷2) to create the differential DDR memory bus clock outputs (MCK and MCK). However, the data rate
is the same frequency as ddr_clk.
The local bus memory controller operates with a frequency equal to the frequency of csb_clk. Note that
lbc_clk is not the external local bus frequency; lbc_clk passes through the LBC clock divider to create the
external local bus clock outputs (LSYNC_OUT and LCLK[0:2]). The LBC clock divider ratio is
controlled by LCRR[CLKDIV]. See the “LBC Bus Clock and Clock Ratios” section in the MPC8323E
PowerQUICC II Pro Communications Processor Reference Manual for more information.
In addition, some of the internal units may be required to be shut off or operate at lower frequency than
the csb_clk frequency. These units have a default clock ratio that can be configured by a memory mapped
register after the device comes out of reset. Table 56 specifies which units have a configurable clock
frequency. Refer to the “System Clock Control Register (SCCR)” section in the MPC8323E PowerQUICC
II Pro Communications Processor Reference Manual for a detailed description.
NOTE
Setting the clock ratio of these units must be performed prior to any access
to them.
Table 57 provides the operating frequencies for the 8323E PBGA under recommended operating
conditions (see Table 2).
Table 56. Configurable Clock Units
Unit
Default Frequency
Options
Security core, I2C, SAP, TPR
csb_clk
Off,
csb_clk/2, csb_clk/3
PCI and DMA complex
csb_clk
Off,
csb_clk
Table 57. Operating Frequencies for PBGA
Characteristic1
Max Operating Frequency
Unit
e300 core frequency (
core_clk)333
MHz
Coherent system bus frequency (
csb_clk)133
MHz
QUICC Engine frequency (
ce_clk)200
MHz
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| KMPC8343CVRAGDB | 功能描述:微處理器 - MPU 8347 PBGA NOPB W/O ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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| KMPC8343CZQAGDB | 功能描述:微處理器 - MPU 8347 PBGA W/O ENC W/ PB RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8343ECVRAGDB | 功能描述:微處理器 - MPU 8347 PBGA NOPB W/ ENC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時(shí)鐘頻率:536 MHz 程序存儲(chǔ)器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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