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| 型號： | KMPC8349ZUALFB |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 73/87頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MPU PWRQUICC II 672-TBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC83xx |
| 處理器類型： | 32-位 MPC83xx PowerQUICC II Pro |
| 速度： | 667MHz |
| 電壓： | 1.3V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 672-LBGA |
| 供應(yīng)商設(shè)備封裝： | 672-TBGA（35x35） |
| 包裝： | 托盤 |
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MPC8349EA PowerQUICC II Pro Integrated Host Processor Hardware Specifications, Rev. 13
Freescale Semiconductor
75
Thermal
20.2
Thermal Management Information
For the following sections, PD = (VDD × IDD) + PI/O where PI/O is the power dissipation of the I/O drivers.
See Table 5 for I/O power dissipation values.
20.2.1
Estimation of Junction Temperature with Junction-to-Ambient
Thermal Resistance
An estimation of the chip junction temperature, TJ, can be obtained from the equation:
TJ = TA + (RθJA × PD)
where:
TJ = junction temperature (°C)
TA = ambient temperature for the package (°C)
RθJA = junction-to-ambient thermal resistance (°C/W)
PD = power dissipation in the package (W)
The junction-to-ambient thermal resistance is an industry-standard value that provides a quick and easy
estimation of thermal performance. Generally, the value obtained on a single-layer board is appropriate for
a tightly packed printed-circuit board. The value obtained on the board with the internal planes is usually
appropriate if the board has low power dissipation and the components are well separated. Test cases have
demonstrated that errors of a factor of two (in the quantity TJ –TA) are possible.
20.2.2
Estimation of Junction Temperature with Junction-to-Board
Thermal Resistance
The thermal performance of a device cannot be adequately predicted from the junction-to-ambient thermal
resistance. The thermal performance of any component is strongly dependent on the power dissipation of
surrounding components. In addition, the ambient temperature varies widely within the application. For
many natural convection and especially closed box applications, the board temperature at the perimeter
Junction-to-package natural convection on top
ψ
JT
1
°C/W
6
Notes:
1. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board)
temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal
resistance.
2. Per SEMI G38-87 and JEDEC JESD51-2 with the single-layer board horizontal.
3. Per JEDEC JESD51-6 with the board horizontal, 1 m/s is approximately equal to 200 linear feet per minute (LFM).
4. Thermal resistance between the die and the printed-circuit board per JEDEC JESD51-8. Board temperature is measured on
the top surface of the board near the package.
5. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method
1012.1).
6. Thermal characterization parameter indicating the temperature difference between package top and the junction temperature
per JEDEC JESD51-2. When Greek letters are not available, the thermal characterization parameter is written as Psi-JT.
Table 63. Package Thermal Characteristics for TBGA (continued)
Characteristic
Symbol
Value
Unit
Notes
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