參數(shù)資料
型號(hào): KMPC8358ZQAGDGA
廠商: Freescale Semiconductor
文件頁數(shù): 59/95頁
文件大?。?/td> 0K
描述: IC MPU POWERQUICC II 668-PBGA
標(biāo)準(zhǔn)包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 400MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 668-BBGA 裸露焊盤
供應(yīng)商設(shè)備封裝: 668-PBGA-PGE(29x29)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
62
Freescale Semiconductor
HDLC, BISYNC, Transparent, and Synchronous UART
19.2
HDLC, BISYNC, Transparent, and Synchronous UART AC Timing
Specifications
Table 61 and Table 62 provide the input and output AC timing specifications for HDLC, BISYNC,
transparent, and synchronous UART protocols.
Table 61. HDLC, BISYNC, and Transparent AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tHIKHOV
0
11.2
ns
Outputs—External clock delay
tHEKHOV
1
10.8
ns
Outputs—Internal clock high impedance
tHIKHOX
-0.5
5.5
ns
Outputs—External clock high impedance
tHEKHOX
18
ns
Inputs—Internal clock input setup time
tHIIVKH
8.5
ns
Inputs—External clock input setup time
tHEIVKH
4—
ns
Inputs—Internal clock input hold time
tHIIXKH
1.4
ns
Inputs—External clock input hold time
tHEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
Table 62. Synchronous UART AC Timing Specifications1
Characteristic
Symbol2
Min
Max
Unit
Outputs—Internal clock delay
tUAIKHOV
0
11.3
ns
Outputs—External clock delay
tUAEKHOV
114
ns
Outputs—Internal clock high impedance
tUAIKHOX
011
ns
Outputs—External clock high impedance
tUAEKHOX
114
ns
Inputs—Internal clock input setup time
tUAIIVKH
6—
ns
Inputs—External clock input setup time
tUAEIVKH
8—
ns
Inputs—Internal clock input hold time
tUAIIXKH
1—
ns
Inputs—External clock input hold time
tUAEIXKH
1—
ns
Notes:
1. Output specifications are measured from the 50% level of the rising edge of CLKIN to the 50% level of the signal. Timings
are measured at the pin.
2. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tHIKHOX symbolizes the outputs
internal timing (HI) for the time tserial memory clock reference (K) goes from the high state (H) until outputs (O) are invalid (X).
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