參數(shù)資料
型號: KMPC8360ZUAJDG
廠商: Freescale Semiconductor
文件頁數(shù): 3/95頁
文件大?。?/td> 0K
描述: IC MPU PWRQUICC II 740-TBGA
標準包裝: 2
系列: MPC83xx
處理器類型: 32-位 MPC83xx PowerQUICC II Pro
速度: 533MHz
電壓: 1.2V
安裝類型: 表面貼裝
封裝/外殼: 740-LBGA
供應(yīng)商設(shè)備封裝: 740-TBGA(37.5x37.5)
包裝: 托盤
MPC8358E PowerQUICC II Pro Processor Revision 2.1 PBGA Silicon Hardware Specifications, Rev. 3
Freescale Semiconductor
11
Electrical Characteristics
2.1.3
Output Driver Characteristics
Table 3 provides information on the characteristics of the output driver strengths. The values are
preliminary estimates.
2.2
Power Sequencing
This section details the power sequencing considerations for the MPC8358E.
2.2.1
Power-Up Sequencing
MPC8358E does not require the core supply voltage (VDD and AVDD) and I/O supply voltages (GVDD,
LVDD, and OVDD) to be applied in any particular order. During the power ramp up, before the power
supplies are stable and if the I/O voltages are supplied before the core voltage, there may be a period of
time that all input and output pins will actively be driven and cause contention and excessive current. In
order to avoid actively driving the I/O pins and to eliminate excessive current draw, apply the core voltage
(VDD) before the I/O voltage (GVDD, LVDD, and OVDD) and assert PORESET before the power supplies
fully ramp up. In the case where the core voltage is applied first, the core voltage supply must rise to 90%
of its nominal value before the I/O supplies reach 0.7 V, see Figure 4.
Table 3. Output Drive Capability
Driver Type
Output Impedance (
Ω)
Supply Voltage
Local bus interface utilities signals
42
OVDD = 3.3 V
PCI signals
25
PCI output clocks (including PCI_SYNC_OUT)
42
DDR signal
20
36 (half-strength mode)1
1 DDR output impedance values for half strength mode are verified by design and not tested.
GVDD = 2.5 V
DDR2 signal
18
36 (half-strength mode)1
GVDD = 1.8 V
10/100/1000 Ethernet signals
42
LVDD = 2.5/3.3 V
DUART, system control, I2C, SPI, JTAG
42
OVDD = 3.3 V
GPIO signals
42
OVDD = 3.3 V
LVDD = 2.5/3.3 V
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