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參數(shù)資料
| 型號： | KMPC8540PX833LC |
| 廠商： | Freescale Semiconductor |
| 文件頁數(shù)： | 24/24頁 |
| 文件大小： | 0K |
| 描述： | IC MPU PWRQUICC 783-FCPBGA |
| 標(biāo)準(zhǔn)包裝： | 2 |
| 系列： | MPC85xx |
| 處理器類型： | 32-位 MPC85xx PowerQUICC III |
| 速度： | 833MHz |
| 電壓： | 1.2V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 784-BBGA，F(xiàn)CBGA |
| 供應(yīng)商設(shè)備封裝： | 783-FCPBGA（29x29） |
| 包裝： | 托盤 |
MPC8540 PowerQUICC III Integrated Host Processor Product Brief, Rev. 0.1
Freescale Semiconductor
9
MPC8540 Architecture Overview
Multiple-cycle execution unit (MU)
— Four-cycle latency for integer and floating-point multiplication (including integer, fractional, and both
vector and scalar floating-point multiply instructions).
— Variable-latency divide: 4, 11, 19, and 35 cycles for all Book E, SPE, and SPFP divide instructions. Note
that the MU allows divide instructions to bypass the second two MU pipeline stages, freeing those
stages for other MU instructions to execute in parallel.
— Four-cycle floating-point multiply
— Four-cycle floating-point add and subtract
Signal processing engine APU (SPE APU). The SIMD capability provided by the 64-bit execution units
(MIU, LSU, SIU1) is not a separate execution unit. The hardware that executes 32-bit Book E instructions
also executes the lower half of 64-bit SPU instructions.
— Single-cycle integer add and subtract
— Single-cycle logical operations
— Single-cycle shift and rotate
— Four-cycle integer pipelined multiplies
— 4-, 11-, 19-, and 35-cycle integer divides
— Four-cycle single instruction multiple data (SIMD) pipelined multiply-accumulate (MAC)
— 64-bit accumulator for MAC operations
— Single-precision floating-point operations
Load/store unit (LSU)
— Three-cycle load latency
— Fully pipelined
— Four-entry load queue allows up to four load misses before stalling
— Can continue servicing load hits when load queue is full
— Six-entry store queue allows full pipelining of stores
Cache coherency
— Bus support for hardware-enforced coherency (bus snooping)
Core complex bus (CCB)
— High-speed, on-chip local bus with data tagging
— 32-bit address bus
— 60x-like address protocol with address pipelining and retry/copyback
— Two general-purpose read data, one write data bus
— 128-bit data plus parity/tags (each data bus)
— Supports out-of-order reads, in-order writes
— Little to no data bus arbitration logic required for native systems
— Easily adaptable to 60x-like environments
— Supports one-level pipelining of addresses with address-retry responses
Extended exception handling
— Supports Book E interrupt model
– Interrupt vector prefix register (IVPR)
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| KMPC8540PXAQFB | 功能描述:微處理器 - MPU PQ 3 DRACO-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8540VT667LB | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8540VT667LC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8540VT833LB | 功能描述:微處理器 - MPU PQ 3 8540DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| KMPC8540VT833LC | 功能描述:微處理器 - MPU PQ 3 8540-DRACOM RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數(shù)據(jù)總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數(shù)據(jù) RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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